Hello, everybody. I'm currently designing a operational amplifier, and I'm using cascode miller compensation. The open loop simulation results show a 4 MHz GBW and 69° phase margin. However, for a voltage follower configuration, when I run a transient simulation for a step input signal, I'm seeing ringing. Why? The github repo is at https://github.com/lhrodovalho/sky130_rodovalho_ip__lpopamp/ and the testbenches are in the xschem folder.

Hello, i am trying to plot with internal waveform graph two signal in a transient simulation. I already do this things several time, but in this testbench is not working. The file is generated, i con plot the signal with terminal, but when i want to load .raw file appear... "raw_read(): failed to open file /home/roberto/.xschem/simulations/tb_schmitt_strigger.raw for reading". Any idea? .temp = 27 .control save all tran 1n 6u plot v(IN) v(OUT) write schmitt_trigger_tran.raw .endc

Hi, I am new to efabless tape out process and the use of open source tools. I have designed a two stage opamp to understand the design and tape out process for analog circuits. While running precheck locally, the GPIO-Defines check is failing. I have edited the user_defines.v file as suggested but the error is still present. Please see the attached user_define.v file and precheck log. Moreover, the precheck is not running LVS. The caravel was initially installed for digital designs (MPW8) with user_project_wrapper but I cloned an user_analog_project_wrapper and followed the steps with the old CARAVEL_ROOT path. Is that creating the issue? Please help me with the issue.

Hello everyone. I'm new to the open pdk (skywater130 pdk) technology and I'm currently facing some simulation issues. After installation I tried designing a simple CMOS inverter(screenshot of the schematics is attached) to get used to the software commands and interface. When I tried simulation I got this error message:

Error: Could not find include file ../../../libs.ref/sky130_fd_pr/spice/sky130_fd_pr__nfet_01v8__tt.pm3.spice
Error: Could not find include file ../../libs.ref/sky130_fd_pr/spice/sky130_fd_pr__res_generic_nd.model.spice
Error: Could not find include file ../../../../libs.ref/sky130_fd_pr/spice/sky130_fd_pr__special_nfet_latch__mismatch.corner.spice
Note: Compatibility modes selected: hs

Circuit: ** sch_path: /home/emmanuel-innocent/designs/examples/inverter.sch
Error: unknown subckt: xm1 inv_out vin 0 0 sky130_fd_pr__nfet_01v8 l=0.15 w=1 nf=1 ad={int((nf+1)/2)*w/nf*0.29} as={int((nf+2)/2)*w/nf*0.29} pd={2*int((nf+1)/2)*(w/nf+0.29)} ps={2*int((nf+2)/2)*(w/nf+0.29)} nrd={0.29/w} nrs={0.29/w} sa=0 sb=0 sd=0 mult=1 m=1
    Simulation interrupted due to error!

After I got the message I decided to check the

spice

subfolder in the skywater130 primitive device folder through the path

/usr/local/share/pdk/libs.ref/sky130_fd_pr/spice

and I discovered that the

spice

sub-folder that's suppose to be in the

sky130_fd_pr

folder is missing. Maybe that's why ngspice raised the "could not find include file" error. This seems to have been caused perhaps because one step or the other was skipped during installation of the pdk. But I can say for sure I did not make any mistake during installation because I followed the instructions from the open PDK website ( Open_PDKs ) to compile and install from source. In fact, I've correctly uninstalled and re-installed the pdk about 3 times now. But I still get similar error. Even when I tried running the pdk simulation examples I still get similar error with model or spice file not being found. Please I need your assistance to get this problem solved so I can start working with the PDK. Thank you.

hi, now I'm getting this error in my project in open lane "[ERROR]: There are hold violations in the design at the typical corner", this error point me to a file with the timings. What I need to change to fix the hold violation error?, increment target density, bigger chip, etc ..

In a 3-well process (nwell, pwell, deep nwell) there are 5 types of diodes. pdiff - nwell, pwell - ndiff, psub - nwell, pwell - deep nwell, psub - deep nwell (if psub is not virtually split, psub - nwell and psub - deep nwell are electrically equivalent). From what I can see, the magic extraction rules only handle pdiff - nwell and pwell - ndiff. @User Is this correct?

Is there a document contain the technology parameters of mosfets of sky130 like uncox , lambda , etc. ? please provide a link.

Is there any reason why generic resistors are not recommended for analog applications? https://antmicro-skywater-pdk-docs.readthedocs.io/en/latest/rules/device-details.html#id48

hundreds of these: Warning: Macro not found in LEF file: sky130_fd_sc_hd__decap_3 (line=118, cell=, file=spm.def) Warning: Macro not found in LEF file: sky130_fd_sc_hd__tapvpwrvgnd_1 (line=119, cell=, file=spm.def)

Hello, I encountered an LVS error. It seems the error is related to mismatched pin names of MOSFETs. Done anyone know how to solve it?