Hi All, I am trying to design an ESD protection circuit since I am planning to use 11 analog pins in caravan wrapper which has no ESD protection. I tried simulating the available diode model diode_pw2nd_05v5 using the combined models. I changed the device name from D to XD. After simulation, I am getting a forward voltage of around

1.78V

required to turn on the diode (image is attached). Is that result correct or am I doing something wrong? Moreover, I can not find any ESD specific devices other than some nfet and there as well I can not find any difference in layout. Can anyone please help with what devices to use and how to simulate it properly. I also tried simulating

test_esd

circuit provide by @Stephen Schippers. I simulation is not running properly. Can anyone please help me with the issue?

your diode has 1e11 as area, this is equivalent to a 0.1um2 device. A small 1um x 1um diode has area=1e12 and perimeter=4e6 Nobody knows why a different scale is used for diodes If you then think

DC

sim is ok try then to run a

tran

analysis. You will realize the device does not work at all. For some reason diode models are broken

Hi @Stephen Schippers I did the transient simulation and it is wrong. Can you please suggest me a way to design and simulate ESD protection circuit properly? Is there any way?

In the normal BSIM spice model the ggnmos will not work because the parasitic bipolar is not modeled. Some pdks provide verilog-A models of ggnmos, but those are usually based on measurements or TCAD. Simulation of ESD structures usually require Transistor CAD (TCAD). A bit more info at https://m.youtube.com/watch?v=6bqHO1iIJw0&list=PLybHXZ9FyEhZfwQTKrLhm6ZZm4IDfGGla&index=4&t=967s

HI @carsten. Thank you so much for your answer. The video was amazing, explained the working of GGNMOS very well. So if I want to put ESD protection at my pins using SKY130 PDK, what is the correct way for simulation since I can not simulate ggnmos or diode in current setup. I have an ESD circuit designed. I will attach the schematic but I can not simulate its parameters correctly.

@naina singhal the issue with diode models is long standing, and it seems there is not much pressure in the right places to get these models working. I don't think this is a titanic work, since PN junctions are not difficult to describe, at least to a reasonable approximation. May be @Tim Edwards can add some insightful comments on this.

@Stefan Schippers: The issue with the diodes is that they are level 3 diodes, where "level 3" is some proprietary Cadence thing (if I recall correctly); Holger Vogt implemented the basic principle that the level 3 model is based on physical dimensions instead of a scaling factor. But there is another twist to the models in that they can be described either with physical dimensions or a scaling factor, so all the values change radically based on a single parameter. My gut feeling is that the weird dimensions are for the purpose of normalizing the coefficients for the physical dimensions to the coefficients used with the scale factor, maybe for the purpose of making them work on simulators that don't support level 3 diodes.

@Tim Edwards Yes the problem with level=3 for diodes is the primary problem. Even if in DC the diode shows decent I/V characteristic (with the area=1e12, perim=4e6 parameters) there is no such decent behavior in transient analysis. in .tran diode is a perfect open when reverse biased (I/V = GMIN) and a perfect short on forward biasing (kind of a perfect, ideal diode that everyone would like to have).

I don't think there is a "correct" way of simulating ESD if the model does not support it. I have not checked the sky130 kit, but if there are esd diodes in a pdk, or ggnmos, then skywater may have documented the peak current for the component (i.e 1.3 A for 2kV HBM). You put the device in your schematic, and you simulate to check that the circuit work under normal conditions. You don't simulate an ESD event, you tapeout, and you hope that it works.

For a test chip, like the Caravel chip where the pads are not ESD protected but this is not going to be a production part, any ESD structure will help keep the chip from being ultra-sensitive; no implementation will be particularly good because the user project prevents the ESD circuits from being directly under the pads where they optimally ought to be placed.

Ok. Thank you so much @Stephen Schippers @Tim Edwards @carsten for explanation. I will use GPIO pads (with ESD protection) and turn-off the buffers connected to them. Moreover, I will connect VDD to one of the three pads with clamp circuits in caravan wrapper. Will that be ok? Is there any way to do post layout simulation with pads and everything? I want to simulate the leakage current in ESD.

Tim, You worked on ESD Fets for the analog pads in another application for Behzad IIRC. Have you shared that ESD work publicly and would it help solve Naina's issue? Also does she need caravan or could she use caravel?(Avoiding this issue completely.)

In the layouts I have, the ESD FETs are integrated into the I/O bus structure. But you can look in the

sky130_fd_io

library at the cell

sky130_fd_io__minesd_pad_and_buses

for the ESD structure, which is made of two components from the same library,

sky130_ef_io__esd_pdiode_11v0_single

and

sky130_ef_io__ ndiode_11v0_single

. Those are the devices you want for ESD protection. One each of these is minimal ESD protection; the "standard" ESD on a pad is four or maybe six of them in parallel.

Thank you @Andrew Wright for help. @Tim Edwards, I read several posts regarding ESDs on slack. In one you mentioned that even if the user designs the ESD protection circuit (for 8 analog pads in caravan), It will be around 200um away from the pad which makes the ESD protection less effective. Therefore, I am planning to use GPIO pads in analog mode since there specifications match with the characteristics of the design. The issue I am facing is regarding the simulation of these pads. I need to get the leakage current through ESD protection circuit. One of the major specification of my design is very low current consumption. But I am unable to simulate any diode from sky130 PDK due to issue in its model. Is there any way to simulate the overall circuit (analog) with pad and ESD or not? I tried extracting the parasitic of the pad but I got a segmentation fault from the magic. Moreover, should I put any secondary ESD protection while using the GPIO pads?