I have a black boxed inverter macro that has vdd and gnd as power pins.I connected these pins with vdda1 and vssa1 as I am using 2 analog pins as input and output.Then I got an error at step 40 of hardening user_pro_example that no pins are marked as POWER or ground in LEF.Then I added in the LEF file "USE POWER ;"and "USE GROUND :"and got rid of the error.Now it is failing LVS at step 42.In layout I have vdd and gnd pins, but not explicitly defined as power pins.I have attached the snapshot of LEF and verilog file.Please help me to fix the error.

can you share

42-lvs.lef.log

?

Thank you for reply.Here is the file

Thanks! Can you share

openlane/user_proj_example/runs/24_02_27_21_33/logs/signoff/42-user_proj_example.lef.lvs.log

also? You can see that the layout has 2 more nets than the verilog at the top level.

42-user_proj_example.lef.lvs.log

Looking at the log file, you can see the device counts match but not the net counts. The layout has 2 more nets than the source. The trick is to find out what doesn’t match.

Subcircuit summary:
Circuit 1: user_proj_example               |Circuit 2: user_proj_example               
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__tapvpwrvgnd_1 (101555->1) |sky130_fd_sc_hd__tapvpwrvgnd_1 (101555->1) 
sky130_ef_sc_hd__decap_12 (405248->1)      |sky130_ef_sc_hd__decap_12 (405248->1)      
sky130_fd_sc_hd__fill_1 (101902->1)        |sky130_fd_sc_hd__fill_1 (101902->1)        
sky130_fd_sc_hd__decap_6 (99723->1)        |sky130_fd_sc_hd__decap_6 (99723->1)        
sky130_fd_sc_hd__decap_8 (551->1)          |sky130_fd_sc_hd__decap_8 (551->1)          
sky130_fd_sc_hd__decap_3 (2951->1)         |sky130_fd_sc_hd__decap_3 (2951->1)         
sky130_fd_sc_hd__diode_2 (16->7)           |sky130_fd_sc_hd__diode_2 (16->7)           
sky130_fd_sc_hd__decap_4 (551->1)          |sky130_fd_sc_hd__decap_4 (551->1)          
sky130_fd_sc_hd__buf_12 (6)                |sky130_fd_sc_hd__buf_12 (6)                
sky130_fd_sc_hd__fill_2 (17->1)            |sky130_fd_sc_hd__fill_2 (17->1)            
sky130_fd_sc_hd__nor2_1 (2)                |sky130_fd_sc_hd__nor2_1 (2)                
sky130_fd_sc_hd__dfxtp_4 (3)               |sky130_fd_sc_hd__dfxtp_4 (3)               
inverter (1)                               |inverter (1)                               
sky130_fd_sc_hd__clkbuf_16 (4)             |sky130_fd_sc_hd__clkbuf_16 (4)             
sky130_fd_sc_hd__conb_1 (4)                |sky130_fd_sc_hd__conb_1 (4)                
sky130_fd_sc_hd__clkbuf_2 (1)              |sky130_fd_sc_hd__clkbuf_2 (1)              
sky130_fd_sc_hd__dlygate4sd3_1 (2)         |sky130_fd_sc_hd__dlygate4sd3_1 (2)         
sky130_fd_sc_hd__dfxtp_1 (1)               |sky130_fd_sc_hd__dfxtp_1 (1)               
sky130_fd_sc_hd__dlymetal6s2s_1 (1)        |sky130_fd_sc_hd__dlymetal6s2s_1 (1)        
sky130_fd_sc_hd__buf_1 (1)                 |sky130_fd_sc_hd__buf_1 (1)                 
sky130_fd_sc_hd__and3b_1 (1)               |sky130_fd_sc_hd__and3b_1 (1)               
sky130_fd_sc_hd__a31o_1 (2)                |sky130_fd_sc_hd__a31o_1 (2)                
sky130_fd_sc_hd__nand4_1 (1)               |sky130_fd_sc_hd__nand4_1 (1)               
sky130_fd_sc_hd__a21oi_1 (2)               |sky130_fd_sc_hd__a21oi_1 (2)               
sky130_fd_sc_hd__o21a_1 (1)                |sky130_fd_sc_hd__o21a_1 (1)                
Number of devices: 48                      |Number of devices: 48                      
Number of nets: 44 **Mismatch**            |Number of nets: 42 **Mismatch**

Here you can see that your inverter has not been connected to power. (layout is on the left, source is on the right)

Net: inverter/vdd                          |Net: dummy_40                              
  inverter/vdd = 1                         |  sky130_fd_sc_hd__conb_1/proxyHI = 1      
...                                   
                                           |                                           
Net: inverter/gnd                          |(no matching net)                          
  inverter/gnd = 1                         |

Can you share your config file? Power is not normally routed like other signals.

I changed magic file, identified power and ground pin as power and ground in the magic file. Then I used the lef file and gds.Still, I am having the same issue.Beside,it has an error at step 6"[ERROR]: Can't find vdda1 and vssa1 domain. Make sure that both exist in vccd1 and vssd1." Here are my latest config,logs, and errors.It will be nice to get suggestion in this regard

Try adding

vdda1

to

VDD_NETS

and

vssa1

to

GND_NETS

. Also change your

FP_PDN_MACRO_HOOKS

line to

"FP_PDN_MACRO_HOOKS": ["inverter vdda1 vssa1 vdd gnd"],

Thank you for your response.I just started running changing to "FP_PDN_MACRO_HOOKS": ["inverter vdda1 vssa1 vdd gnd"],.It showed the same error at step 6,but still running.

Try adding

vdda1

to

VDD_NETS

and

vssa1

to

GND_NETS

.

Did you do this?

yes,I am running it now.It shwed the same error at step 6.but still running.Trying "FP_PDN_MACRO_HOOKS": ["inverter vdda1 vssa1 vdd gnd"] was failed at LVS again.

Can you share your config.json, lef, and verilog files?

Hay,I checked the gds.I think the issue with lvs is that macro is too small to get connected with power rails.However,still not recognizing vssa1 and vdda1 is an issue.Along with these files ,I am sharing GDs as well. Could you plz tell me where analog power rails get connected?

The config file still only has the digital power defined. Try adding

vdda1

and

vssa1

like this

"VDD_NETS": [
        "vccd1", "vdda1"
    ],
    "GND_NETS": [
        "vssd1", "vssa1"
    ],

And then check the placement to ensure that the cell will intersect the necessary power rails.

This is showing syntax error.I also tried "FP_PDN_MACRO_HOOKS": ["inverter", ["vccd1", "vdda1"], ["vssd1", "vssa1"]],Still error in config file.

Not in the

FP_PDN_MACRO_HOOKS

line. Try this config file

{
  "DESIGN_NAME": "user_proj_example",
  "DESIGN_IS_CORE": 0,
  "VERILOG_FILES": [
    "dir::../../verilog/rtl/defines.v",
    "dir::../../verilog/rtl/user_proj_example.v"
  ],
  "EXTRA_LEFS": "dir::macros/lef/*.lef",
  "EXTRA_GDS_FILES": "dir::macros/gds/*.gds",
  "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
  "FP_PDN_VERTICAL_LAYER": "met4",
  "FP_PDN_HORIZONTAL_LAYER": "met3",
  "VERILOG_FILES_BLACKBOX": [
    "dir::../../verilog/rtl/inverter.v"
  ],
  "FP_PDN_MACRO_HOOKS": [
    "inverter",
    "vdda1",
    "vssa1",
    "vdda1",
    "vssa1"
  ],
  "CLOCK_PERIOD": 25,
  "CLOCK_PORT": "wb_clk_i",
  "CLOCK_NET": "<http://counter.net|counter.net>",
  "FP_SIZING": "absolute",
  "DIE_AREA": "0 0 150 250",
  "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
  "MAX_TRANSITION_CONSTRAINT": 1,
  "MAX_FANOUT_CONSTRAINT": 16,
  "PL_TARGET_DENSITY": 0.4,
  "PL_RESIZER_SETUP_SLACK_MARGIN": 0.4,
  "GLB_RESIZER_SETUP_SLACK_MARGIN": 0.2,
  "GLB_RESIZER_HOLD_SLACK_MARGIN": 0.2,
  "PL_RESIZER_HOLD_SLACK_MARGIN": 0.4,
  "MAGIC_DEF_LABELS": 0,
  "SYNTH_BUFFERING": 0,
  "RUN_HEURISTIC_DIODE_INSERTION": 1,
  "HEURISTIC_ANTENNA_THRESHOLD": 110,
  "GRT_REPAIR_ANTENNAS": 1,
  "VDD_NETS": [
    "vccd1",
    "vdda1"
  ],
  "GND_NETS": [
    "vssd1",
    "vssa1"
  ],
  "IO_SYNC": 0,
  "BASE_SDC_FILE": "dir::base_user_proj_example.sdc",
  "RUN_CVC": 1,
  "pdk::sky130*": {
    "FP_CORE_UTIL": 45,
    "RT_MAX_LAYER": "met4",
    "scl::sky130_fd_sc_hd": {
      "CLOCK_PERIOD": 25
    },
    "scl::sky130_fd_sc_hdll": {
      "CLOCK_PERIOD": 10
    },
    "scl::sky130_fd_sc_hs": {
      "CLOCK_PERIOD": 8
    },
    "scl::sky130_fd_sc_ls": {
      "CLOCK_PERIOD": 10,
      "SYNTH_MAX_FANOUT": 5
    },
    "scl::sky130_fd_sc_ms": {
      "CLOCK_PERIOD": 10
    }
  },
  "pdk::gf180mcuC": {
    "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
    "CLOCK_PERIOD": 24,
    "FP_CORE_UTIL": 40,
    "RT_MAX_LAYER": "Metal4",
    "SYNTH_MAX_FANOUT": 4,
    "PL_TARGET_DENSITY": 0.45
  }
}

Thank you that error is gone,but another error related to vdda1 in IRDROP at step 35

If there’s a gds file created, can you share that?

No GDS file is created

Sounds like vdda1 is not connected to anything. Can you verify with odb data?

This is the file from tmp.

Can you share your

verilog/rtl/user_proj_example.v

file? The odb is missing

vssa1

and

vdda1

power rails.

user_proj_example.v,inverter.v,16-user_proj_example.odb,18-user_proj_example.odb

ok. how about

verilog/gl/user_proj_example.v

? Is that available? Maybe it’s somewhere in the

runs

directory.

I got it from results/synthesis

The

vssa1

and

vdda1

power are missing from that netlist.

yes,thats what I saw as well.What can be the reason?

And the inverter is connected to digital power.

inverter inverter (.A(net1),
    .Y(net3),
    .vdda1(vccd1),
    .vssa1(vssd1));

user_project_wrapper.v,user_proj_example.v

Those verilog files look good to me. They’re in your

verilog/rtl

directory, right?

Yes

I doubt that it will make a difference, but generally the

FP_PDN_MACRO_HOOKS

is one string

"FP_PDN_MARCO_HOOKS": ["inverter vdda1 vssa1 vdda1 vssa1"],

Thats what I also came to know from my lab seniors who did last tape out.But they did using vccd1.no analog pins.I was looking IR DROP related configuration here..https://openlane.readthedocs.io/en/latest/reference/configuration.html

I don’t think the

VSRC_LOC_FILE

file is related to power routing. Maybe you need to use a modified

pdn.tcl

file. @Kareem Farid could you help on this one? In order to create a macro with mulltiple power and ground rails, do you need to modify

pdn.tcl

? It looks like the synthesized verilog is connecting the analog macro to digital power, but that’s not related to the pdn, is it?

@Mitch Bailey @Kareem Farid or anyone else ,any thoughts on fixing the issue?

@Md Omar Faruque Can you open up an issue OpenLane github with the source files? It would be easier to follow and help there.

Thank you for your response.I have created the issue.Here is the link https://github.com/efabless/caravel_user_project/issues/356

Thanks. I will take a look tomorrow

@Md Omar Faruque have you shared all the input files? For example,

macro.cfg

and

pin_order.cfg

?

@Mitch Bailey Yes,I have already uploaded macro.cfg and pin_order.cdg

what is the OpenLane version that you are using?

It should be openlane 1 as it is not openlane-2

which version of OpenLane1?

@Kareem Farid I get the same error with openlane 2023.07.19-1.

@Mitch Bailey This is the version I used as well.

I think I am getting somewhere. I have enabled

FP_PDN_SKIPTRIM

and moved the macro to

40 150

and I am seeing

vssa1

and

vdda1

getting connected to the macro. I am waiting to see the rest of the flow

I had the issue 1st then I extended the power rails and get rid of it for vccd1.

I added to the above:

"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
    "LVS_CONNECT_BY_LABEL": true

and it got it passing.

Thank you ,yes it got passed now.But now it is showing LVS error while hardening user_project_wrapper. The issue is again with vdda1 and vssa1.I enabled LVS_CONNECT_BY_LABEL. When not worked out , tried to use PDN_MACRO_CONNECTIONS as well.

@Md Omar Faruque can you share the resultant GDS?

@Md Omar Faruque Try

"FP_PDN_MACRO_HOOKS": ["mprj vccd1 vssd1 vccd1 vssd1,", "mprj vdda1 vssa1 vdda1 vssa1"],

Where did

PDN_MACRO_CONNECTIONS

come from? I couldn’t find it in the documentation.

Adding "FP_PDN_MACRO_HOOKS": ["mprj vccd1 vssd1 vccd1 vssd1,", "mprj vdda1 vssa1 vdda1 vssa1"], solved the isseu and the flow was completed.However,while I am doing precheck it again failed LVS and klayout feol.While checking the klayout feol issue,I found https://web.open-source-silicon.dev/t/424631/hi-what-is-a-klayout-feol-error-from-the-precheck-i-looked-o I changed the XML file based on it.Besides,I checked the lvs.log ,it looks fine to me.

openlane LVS has all the subcircuits black-boxed, while precheck LVS allows a full device level LVS. However, you need to set up the

lvs/user_project_wrapper/lvs_config.json

file. There should be instructions in the precheck repo README, but if you have problems, let me know. You could share

precheck_results/<tag>/logs/LVS_check.log

and

precheck_results/<tag>/outputs/reports/lvs.report

for advice on a specific problem.

Thank you .I will go through the README now . ..Sorry,my bad

@Md Omar Faruque One problem is that the inverter source is not specified. Without this, you get the following message

Circuit 2 cell inverter is a black box; will not flatten Circuit 1

If you create a spice netlist for the inverter from an xschem schematic, you can add that to the lvs_config.json file.

"LVS_SPICE_FILES": [ 
    "$UPRJ_ROOT/xschem/simulation/inverter.spice"
]

The second problem that you’re seeing is that

vssd1

and

vssa1

are shorted through the substrate in the layout but separate in the source. If you absolutely what these 2 nets separated, then you’ll want to put the analog inverter in a dnwell region surrounded with nwell and connected to

vdda1

.

Net: vssd1                                                                        |Net: vssd1                                                                        
  sky130_fd_sc_hd__diode_2/VGND = 6                                               |  sky130_fd_sc_hd__diode_2/VGND = 6                                               
...                                               
  sky130_fd_sc_hd__conb_1/VGND = 4                                                |  sky130_fd_sc_hd__conb_1/VGND = 4                                                
  inverter/vssa1 = 1                                                              |                                                                                  
                                                                                  |                                                                                  
(no matching net)                                                                 |Net: vssa1                                                                        
                                                                                  |  inverter/vssa1 = 1

If you’re ok with

vssd1

and

vssa1

being connected through psubstrate because it has a high resistance and you don’t think there will be an effect on your circuit, you can cover the inverter with

substrateCut

(also know as

isosub

)

81/53

. This will isolate the regions during extraction.

@Mitch Bailey , Thank you, and sorry for the late response. I was having some drc error for hardening user project example ,while separating the macro. Though my macro individually had no issue.Later,I found the issue was due to not labeling pins with bigger box. However,after using paint isosub and adding spice file,the macro has no lvs error in precheck,but klayout_feol still remains.While doing precheck,it also has drc violalation,though no drc errors are shown in user_project_wrapper.

@Md Omar Faruque I’ll take a look tomorrow.

cvc.error.gz,klayout_feol_check.xml

The drc results are showing overlapping

nsdm

and

psdm

. Was the

inverter

layout created in magic or klayout?

The layout was created in magic.

magic should automatically create

nsdm

and

psdm

layers on gds out. Can you share

user_proj_example.mag

and

inverter.mag

?

user_proj_example.mag,inverter.mag

@Md Omar Faruque Thanks. I was expecting the mag files to contain references to the gds files. Let me check with the architects.

@Mitch Bailey I found that mvntransistor is used for higher voltage.It should fix the ERC check failure right?

@Md Omar Faruque Yes, it should fix the ERC electrical overstress issue. You also need to be careful about input. If you input a 1.8V signal into a 3.3V inverter, both the pmos and the nmos will be on at the same time.