One possibility: lay out a grid containing many rows that each consist of many instances of a particular cell, with all layers present as normal, and then mount it in a grinding fixture at a slight angle to horizontal, so that grinding it once will give you many different slices through each cell design, at different layers. I don't think SEM works through oxide, so regardless of mask layout, I suspect you'll have to do some sort of grinding or etching anyway as the whole chip will get passivation oxide over it (except for bondpads) and any metal that is not top metal will get inter-layer oxide over it except for where there are vias up to the next higher layer of metal, and it might be DRC-naughty or even impossible to make a stack of massive via holes without actual metal via plugs in them just to expose the lower layers for SEM imaging.