Kunal
05/01/2023, 3:18 PMDavid Bertuch
05/03/2023, 3:38 AMPeter Schmidt-Nielsen
05/04/2023, 6:04 AMALOK PRATAP SINGH
05/04/2023, 12:51 PMguo tang
05/05/2023, 4:59 PMguo tang
05/05/2023, 4:59 PMguo tang
05/05/2023, 5:01 PMTayyeb Mahmood
05/08/2023, 3:15 AMPeter Schmidt-Nielsen
05/09/2023, 10:29 PMALOK PRATAP SINGH
05/10/2023, 5:23 AMTrevor Clarke
05/10/2023, 3:04 PMMatt Liberty
05/10/2023, 5:56 PMAvinash Gupta
05/13/2023, 4:26 AMcalvin
05/13/2023, 6:44 AMBalram Pillai
05/14/2023, 9:10 AMhtamas
05/15/2023, 1:19 PMz-a-p-k-i-n-g
05/16/2023, 10:40 AMPeter Schmidt-Nielsen
05/24/2023, 10:30 PMlibraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_1.spice
):
.subckt sky130_fd_sc_hd__nand2_1 A B VGND VNB VPB VPWR Y
X0 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X1 VPWR B Y VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X2 VGND B a_113_47# VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X3 a_113_47# A Y VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
.ends
Note that sky130_fd_pr__pfet_01v8_hvt
defines its args in the order: drain, gate, source, body. So, FET X0 makes sense as a pull-up for A=0, because its drain is the output. But FET X1 seems backwards, why is VPWR the drain, and Y the source, not the other way around? I have the same confusion with the pull-down stack of X2 and X3, although at least there symmetry is broken between the two FETs. But in the pull-up case I can't see what breaks symmetry between the A and B inputs, and why one FET would be backwards relative to the other.Erik DeBenedictis
05/24/2023, 10:34 PMTomasz Chadzynski
05/27/2023, 1:56 AMChristian Duffee
05/27/2023, 3:12 PM"pdk::sky130*": {
"FP_CORE_UTIL": 45,
"RT_MAX_LAYER": "met4",
"scl::sky130_fd_sc_hd": {
"CLOCK_PERIOD": 25
},
"scl::sky130_fd_sc_hdll": {
"CLOCK_PERIOD": 10
},
"scl::sky130_fd_sc_hs": {
"CLOCK_PERIOD": 8
},
"scl::sky130_fd_sc_ls": {
"CLOCK_PERIOD": 10,
"SYNTH_MAX_FANOUT": 5
},
"scl::sky130_fd_sc_ms": {
"CLOCK_PERIOD": 10
}
Increasing PL_RESIZER_SETUP_SLACK_MARGIN
, PL_RESIZER_SETUP_SLACK_MARGIN
and GLB_RESIZER_SETUP_SLACK_MARGIN
have no effect on my setup violations. My understanding is that the clock is either provided from the PLL or external input, so this would be fine, but I wanted to make sureIslam Elsadek
05/30/2023, 6:57 PMIslam Elsadek
05/30/2023, 6:57 PMRenzo Barraza
05/30/2023, 7:25 PMset_propagated_clock
, but according to manpage that command does not propagate clocks, but changes the clock tree from an ideal network into a network with delays.Minsang Yu
05/31/2023, 7:06 AMAidan Medcalf
05/31/2023, 7:20 PMJeremy Popp
06/06/2023, 1:38 PMJeremy Popp
06/06/2023, 1:41 PMSlackbot
06/06/2023, 6:52 PMDiarmuid Collins
06/08/2023, 8:44 PM