ALIGN Open-Source Tool for Analog Circuit Layout Synthesis: Hands-on Lab-based Training Webinar If you're a circuit designer looking for a more efficient way to synthesize analog circuit layouts, then you won't want to miss this free webinar on the ALIGN open-source tool. Developed by a team of academics and industry professionals, ALIGN is an automatic layout generator that can translate an unannotated SPICE netlist into a GDSII layout in just 24 hours. In this webinar, we'll be discussing how the ALIGN tool works and how it can be used to synthesize the layout for a 4-bit asynchronous up counter. This mixed-signal circuit is designed using xschem and Ngspice tools and features T flip-flops, a ring oscillator, an ADC, and a DAC. The webinar will cover a range of topics related to the ALIGN project, including design specifications, an introduction to ALIGN, installation of ALIGN prerequisites, ALIGN installation, ALIGN SKY130 installation with a buffer example, and pre and post-layout analysis of a ring oscillator and ADC using ALIGN. One of the benefits of ALIGN is that it's an open-source tool, meaning that it's freely available to use and modify. This makes it an excellent resource for designers who are looking for a more customizable and efficient way to synthesize analog circuit layouts. Additionally, the ALIGN tool was jointly developed under the DARPA IDEA program by the University of Minnesota, Texas A&M University, and Intel Corporation, so you know that it's been rigorously tested and optimized for real-world use. Webinar registration from - https://forms.gle/Dh6EKHNv59Wgw1Ku9 Webinar Dates and Timings - 2nd May, 8pm to 9pm IST To enroll in this free webinar and learn more about how ALIGN can help you with your analog circuit layout synthesis, simply click on the link below. We look forward to seeing you there! Once you fill the form, you will receive meeting invitation

Hello, I am running LVS on my circuit design that uses standard cells. However, I am getting some odd net mismatches. Each output pin (labeled Q#) is connected in an identical manner to a the output of a NAND gate, and is then fed into the input of an inverter. These instances are essentially copies of each other, aside from the NAND inputs (which are not causing an issue). For some reason, some of the output nets are matching properly, and some are not. I have attached some snapshots of the netgen output (left side is from schematic, right side is layout). Also, I've included some pictures from magic to show that the output connections are configured in the same manner (QN1 is fine, QN2 is not). I threw in a picture of the schematic, but I don't think it will help much since they are standard cells. Any help is appreciated -- thanks!

I'd like to know propagation/contamination delays for all of the sky130 standard cells, and also setup/hold times for non-combinational components. Is this info somewhere in the PDK files?

Hi all, I plot Phase. Can any one suggest to plot Magnitude ? What code i need to write in ngspice @Stefan Schippers

Hi, everyone. I am trying to build sky130 pdk following instruction from http://opencircuitdesign.com/open_pdks/. Building version http://opencircuitdesign.com/open_pdks/archive/open_pdks-1.0.411.tgz. How long it normally takes? I am doing ./configure --enable-sky130-pdk, then type make. Now the process seems stuck after several hours, use top to check CPU usage, there are two processes magicdnull, using 100% CPU, stuck there for more than one hour. Is it normal? Thanks!

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Are there any docker image there that I can just pull to avoid building it myself? Thanks!

Hi, I need help validation of timing tables of various std lib cells, utilising SPICE simulations. The goal would be to crate a general-purpose timing model for STA. Any help, guidance or reference?

Maybe a silly question, but it should be valid to mirror the sky130 standard cells horizontally, right?

Hi @Stefan Schippers you have design bandgap refrence but while simulation i am getting error

I've been interested lately in single photon detection and SPADs in particular, especially for LIDAR and particle detector applications. I was thinking that it would be great to have some open hardware building blocks for custom SPAD arrays and I'm wondering if sky130 would be a suitable process for this? There are quite a few CMOS SPAD designs in the literature (for example https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4299038/) but I don't know enough of the physics to understand if the sky130 capabilities would be sufficient. Anyone with the physics background want to have a look and see if it's a possibility? If so, I'd be happy to spearhead a group to work on this

In the docs there is now a page for all cells https://skywater-pdk.readthedocs.io/en/main/contents/cell-index.html. The 'x' link to a more detailed description per type.

Hi everyone, I am working on the layout with sky130 pdk, and I want the allowed current density for each metal line interconnect for my design. I tried searching the documentation but couldn't get any information on this. Can anyone help me with this information, or how I can calculate it theoretically? @Stefan Schippers @mehdi

hi everyone may i know is that possible that the sky130 library run in synopsys tools like dc/icc?

Hello all, does anyone have a .tek file of the sky130 pdk for running ASITIC (inductance) simulator?

Does sky130b allow us to build a SONOS-enabled flip-flop standard cell to store a few bits across a power cycle in a fully digital design?

Hi folks, Can anyone please tell me what the "m" parameter associated with passive components like resistors and capacitors in the sky130 node mean? @Tim Edwards

I'm sort of confused what's going on with the SPICE decks for the sky130 standard cells, some of the FETs seem to have drain and source swapped relative to what I'd expect. Take a look at the definition of the 2-input NAND gate (from

libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_1.spice

):

.subckt sky130_fd_sc_hd__nand2_1 A B VGND VNB VPB VPWR Y
X0 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X1 VPWR B Y VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X2 VGND B a_113_47# VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X3 a_113_47# A Y VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
.ends

Note that

sky130_fd_pr__pfet_01v8_hvt

defines its args in the order: drain, gate, source, body. So, FET X0 makes sense as a pull-up for A=0, because its drain is the output. But FET X1 seems backwards, why is VPWR the drain, and Y the source, not the other way around? I have the same confusion with the pull-down stack of X2 and X3, although at least there symmetry is broken between the two FETs. But in the pull-up case I can't see what breaks symmetry between the A and B inputs, and why one FET would be backwards relative to the other.

FETs are symmetric with regards to source and drain. In other words, they work the same even if you reverse source and drain.

Hello everyone, I wanted to ask about the 130 hs cells. There appear to be syntax errors in some of the Verilog models. For example sky130_fd_sc_hs__a22o.behavioral.v line 58 has "wire B2 and0_out;" The port names somehow sneaked into internal wires declarations. This happens in multiple places across the set. Also it seems that the repo for hs cells is already archived. Does that mean no more updates?

Hello, for a sky130 tapeout through efabless, is it alright to increase the PDK frequency in config.json?

"pdk::sky130*": {
        "FP_CORE_UTIL": 45,
        "RT_MAX_LAYER": "met4",
        "scl::sky130_fd_sc_hd": {
            "CLOCK_PERIOD": 25
        },
        "scl::sky130_fd_sc_hdll": {
            "CLOCK_PERIOD": 10
        },
        "scl::sky130_fd_sc_hs": {
            "CLOCK_PERIOD": 8
        },
        "scl::sky130_fd_sc_ls": {
            "CLOCK_PERIOD": 10,
            "SYNTH_MAX_FANOUT": 5
        },
        "scl::sky130_fd_sc_ms": {
            "CLOCK_PERIOD": 10
        }

Increasing

PL_RESIZER_SETUP_SLACK_MARGIN

,

PL_RESIZER_SETUP_SLACK_MARGIN

and

GLB_RESIZER_SETUP_SLACK_MARGIN

have no effect on my setup violations. My understanding is that the clock is either provided from the PLL or external input, so this would be fine, but I wanted to make sure

Hi all,

Is there SRAM that are functional for SkyWater 130, Does OpenRam generate SRAMs that are proved to be working on silicon?

Hi all, What si the command to propagate clocks in OpenSTA? At first I thought it was

set_propagated_clock

, but according to manpage that command does not propagate clocks, but changes the clock tree from an ideal network into a network with delays.

Hi all, is there someone who know why resistor models(ex.sky130_fd_pr__res_high_po_0p69) have 3 ports; r0, r1, b?

How do I properly mark a high-voltage (deep-)N-well, particularly in magic? Do I just cover it with areaid.hvnwell? vhvi.drawing?

Hi, I am trying to finish fixing DRC errors on my top level sky130 layout w/ pre-check. The last two types reported by Magic are [ERROR] - Violation Message 'All nwells must contain metal-connected N+ taps (nwell.4)', [ERROR] - Violation Message 'P-diff distance to N-tap must be < 15.0um (LU.3)' . The challenge I am having is that the locations pointed to in the magic_drc_check.drc.report do not seem to correspond to X,Y (um) feature locations in layout. Any suggestions on this?

Other related question, I am opening the layout in magic -rcfile (volare sk130A.magicrc tech file) and it is not showing any DRC errors. Is there another magicrc file I can load so I can see the nwell.4 and LU.3 errors?

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Hi All! I have just started looking into taping out some test structures on SKY130 with efabless. My 3 main questions right now are: 1.) Does this process offer zero temp co poly resistors? 2.) Does it offer +ve and -ve temp co poly resistors? 3.) Is weak inversion properly modelled for the MOSFETs? I cant find documentation on such items. Thanks for any feedback. Diarmuid