PDK docs says """Length is variable and measured between the front ends of the slot licons.""". And yet the above is extracted as L=1.4 and not L=1.56 (cc @Harald Pretl)

The length of the resistor is where silicide formation is suppressed, usually with an extra layer. Polysilicon is made low resistive (for MOSFET gates) by forming silicide on top. So to form a decent resistance value, no silicide wanted.

Mmm, there is a

poly.res

layer too. But the length of that is 1.52 in the above, yet another number.

@Harald Pretl: The layers defining this resistor are URPM and NPC (nitride poly cut, which removes the TiN), which cover the entire resistor including the contacts. @tnt: This was extracted by magic? It looks like at the time I implemented it I did not have a method for adding the extra length needed to reach the contact cut. I have that method now and will add the adjustment.

@Tim Edwards It was both created by magic using the "device" menu asking for L=1.4 and extracted by magic to spice. The length between

licon

contacts turns out to be 1.56. The length of the

poly.res

( 66/13) is 1.52 and the length between the edge of the

li

zones is 1.4.

@tnt: Thank you for reminding me that the device generator will also need to adjust for the length.

@tnt: That led me down a bit of a rabbit hole. I had added the capability to specify a delta for a parameter value like length some time ago, but in the end I didn't use it, so it hadn't been thoroughly tested. Of course it was broken (the scalefactor got lost between the .ext file and the .spice file). So I have updated magic to version 8.3.441 now, which fixes the scalefactor issue, and I will push an update to the sky130 PDK tomorrow with the correct offsets on the resistor length.

@Tim Edwards Thanks for the quick fix, and sorry for the nerd sniping 😅

Hi @mkk I was trying to upload my design to efabless repo via windows PC but faced this issue. @jeffdi

Hi everyone, I was trying to run the caravel_user_project provided by efabless, the link to the github is https://github.com/efabless/caravel_user_project_analog/tree/main The documentation to this sample project is given in the link https://github.com/efabless/caravel_user_project_analog/blob/main/docs/source/index.rst while running the precheck they are saying that 'Default', 'GPIO-Defines', 'OEB' checks have failed. Can someone please help me to resolve this issue. Thanking you in advance, Milan

Hello, I am wondering if there are any details about the Sky130 fabrication process published? What I am in general interested would be the different doping steps, including: • Order of the doping steps • Doping profiles for each step (or implantation doses and implantation energies etc.) This would be used in the context of TCAD simulations, for fabricating more exotic devices, such as radiation and photon detectors. In the #analog-design channel, there were a few high-level discussions about TCAD in the past (in 2020 or so), but nothing ever transpired. The only slightly relevant information that I could found, was under "Semiconductor Criteria" in the docs: https://skywater-pdk.readthedocs.io/en/main/rules/assumptions.html#process-stack-diagram But there only seem to be information about the P-Well and N-Well doping as two single numbers. Am I correct in assuming, that this type of information is not published by Skywater as part of the PDK?

@Nuno Lourenço has left the channel

I'm a beginner and I'm trying to precheck Efabless and I'm getting the following errors:

[11/03/23 07:31:11 PDT] FAILURE
                3 Check(s) Failed: ['XOR', 'Klayout Pin Label Purposes Overlapping Drawing', 'OEB'] !!!
[11/03/23 07:31:11 PDT] OEB CHECK FAILED
                The design, user_analog_project_wrapper, has OEB violations.

Can someone help me?

Hi.. I was trying to import the sky130_fd_pr__nfet_03v3_nvt model spice file to layout. But I am getting guard rings for each standard cells. I can not remove the guard rings for each component. Is it necessary to keep guard rings for each component.? If not how can I remove that? I tried to draw it manually, but it is getting exported as 1.8v nfet spice file. I need 3.3v nfet. Please suggest a solution.

Hi, I created a simple ring oscillator in magic and when I extracted parasitic RC, I get two pfets with length=0 and width=0. Any ideas on how to prevent these from showing up since I have to comment these devices in order for the ngspice testbench simulation to work. Here is the extraction commands I used and I've attached the resulting spice netlist:

extract do local

extract all

ext2sim labels on

ext2sim

extresist tolerance 10

extresist all

ext2spice lvs

ext2spice cthresh 0.01

ext2spice extresist on

ext2spice

does anyone know why the sky130 hd tap cells have a seemingly-unused psdm region next to the tapped nsdm region in the n-well, and equivalently an unused nsdm next to the psdm in the pwell? (here is n well)

Hi channel. Is my understanding correct that skywater doesn't support CMOS image sensors fabrication? In case I'm wrong, could it produce back-illuminated CIS as well?

hello , I am not able to setup the docker , I am not able to connect vnc server and noVNC , any suggestions ?

I am facing this issue : can't connect to the noVNC . any solution ?

image.png

I am also facing these errors , any solution ?

hi anyone please suggest where can we find the model file of sky130_fd_pr__nfet_03v3_nvt...so that we can use this for designing purpose

Hi, i know how to read the netlist mismatch from Netgen, but i can't read the instance mismatch. I've used interdigitation technique and multifingers on my layout, i think the problems are there, but i can't fint them. #netgen #lvs

Right now is electric installed inside the docker for doing layout using sky130 nm technology ? any please let me know

@John Myers has left the channel

Any help?

Is there anywhere a comprehensive overview of the spice model parameters and their naming?

Hello everyone, I have a question regarding the mismatch/monte carlo models in skywater130. I am trying to make sure my chip has a certain robustness incorparated in the design and to do this I am running a monte carlo simulation on the mismatch models. To me it seems that the tt_mm, ss_mm, etc. models only incorporate a gradual variation, but i can't seem to find much documentation on this matter. I was wondering if the mc model takes a more broader variation into account besides the normal process variation and if there is something like an mm model that incorparates the whole variation range in it's model.

@Eman Hassan has left the channel

Has anyone ever attempted to make transient spice simulations including noise? If so, I would be very grateful for some exchange!