Would it not cause massive DRC violations? e.g. a metal2-metal3 via with no metal 3 over the via would surely throw up errors. I'm guessing that some layers also have different meaning depending on other layers being present/not - sort of like boolean operations being performed between the layers as part of the physics of the manufacturing process. I don't know enough about the process to give concrete examples but I suspect that the layer that makes source/drain implants means something different in NMOS or PMOS devices and also something different where gate poly is present or not present.