Hello everybody, Does the PicoRV32 implemented in caravel only work with the ISA RV32I? or does it have other instructions?

First off, the current version of Caravel (since MPW-one, actually) implements a VexRISC, not the PicoRV32 (over my protests---I really like the PicoRV32). You can ask Mohamed Shalan or maybe Jeff DiCorpo for the exact configuration that is implemented in LiteX, but for the most part you can find that defined in

caravel_mgmt_soc_litex/litex/caravel.py

. The variant in VexRISC terms is called "minimal+debug", and I think the ISA is stock RV32I.