Hi all, I am currently working on an ALU capable ...
# caravel
Hi all, I am currently working on an ALU capable of executing vector instructions, and I would like to simulate the whole caravel project (Caravel + my wrapper project). I have seen the files in the dv folder of the caravel repository (https://github.com/efabless/caravel/tree/main/verilog/dv/caravel) but I don't know how to give some instruction to the RISCV processor, and then simulate it with my wrapper project. Could someone help me with it?
Look at these instructions, not the ones in caravel/verilog/dv: https://github.com/efabless/caravel_user_project/blob/main/docs/source/index.rst#section-quickstart . See the section toward the bottom at "Running Full Chip Simulation". The examples like
have C code that you can follow.
has C code for configuring the GPIO;
have C code for communicating with a project through the "logic analyzer" interface, and
has C code for communicating with a project through the wishbone interface.
Hi Edwards, thanks for your quick answer. I checked those files but there aren't any examples of configuring the RISC-V. I want to compare the clock cycles that take the RISC-V to develop 4 adds vs an add using the vector accelerator. So the question is how can I simulate the RISC-V to perform an add or any other function?
All of the simulations like
are simulating the whole chip, including the VexRISC processor. The programs are written in C and compiled into hex code to run on the (emulated) SPI flash. You may need to use an assembler macro in C to ensure that you know exactly how many addition instructions are being executed. If you have compiled from C, you'll have a
output of the dissassembled code which you can compare against the data being returned from the SPI flash. Be aware that the VexRISC has a very small instruction cache which means that it can run a handful of instructions from memory, but it's hard to know when it's going to run something entirely from instruction cache vs. reading from the SPI flash.
+Thank you, it has been a great help.
Hi, it's me again. Im checking some simulations and I think that the big execution time that I had is related to the SPI flash memory. I ran different matrix addition when the matrix is 8 by 8 (64 additions) the performance of the riscv is "good" but when I change the matrix from 8x8 to 12x12 the performance decreased significantly.
Related to your previous answer I think that due to the large data size, the riscv is taking everything off the flash. This is my suspicion but I would like to know what you think?
If we look at the 12x12 picture the riscv seems to be stuck in an instruction (FEC42703 = lw x14, -17(x8))