Emilio Baungarten
02/10/2023, 5:42 PMTim Edwards
02/10/2023, 7:01 PMverilog/dv/io_ports
have C code that you can follow. io_ports.c
has C code for configuring the GPIO; la_test1
and la_test2
have C code for communicating with a project through the "logic analyzer" interface, and wb_port
has C code for communicating with a project through the wishbone interface.Emilio Baungarten
02/11/2023, 5:30 PMTim Edwards
02/13/2023, 2:41 PMverilog/dv/io_ports
are simulating the whole chip, including the VexRISC processor. The programs are written in C and compiled into hex code to run on the (emulated) SPI flash. You may need to use an assembler macro in C to ensure that you know exactly how many addition instructions are being executed. If you have compiled from C, you'll have a .lst
output of the dissassembled code which you can compare against the data being returned from the SPI flash. Be aware that the VexRISC has a very small instruction cache which means that it can run a handful of instructions from memory, but it's hard to know when it's going to run something entirely from instruction cache vs. reading from the SPI flash.Emilio Baungarten
02/13/2023, 9:23 PMEmilio Baungarten
02/18/2023, 6:43 PMEmilio Baungarten
02/18/2023, 6:45 PMEmilio Baungarten
02/18/2023, 6:46 PMEmilio Baungarten
02/18/2023, 6:50 PM