So |= seems to not work as before

I have replaced the code with this:

and now my tb works again

Hello everyone! Does someone know where is located the caravel layout? To be precise, this layout:

IMG_0139.jpg

Red Caravel

Blue Caravel Memory

Green Your Design

This message was deleted.

Hello, If i want to ensure there is no insulating layer atop my design I can should I add a box on the 76:20 layer and cover the whole area? We will be requesting the bare dies, so the RDL should not be present

also, If I want to add a resistor, can I just draw it on 86:20 / 79:20 (along with 66:20) and up through 66:44?

Hello everyone! I am currently going through the quickstart guide for the Caravel user project. After running the hardening command (make user_proj_example) I end up get error messages after Step 17

[ERROR]: during executing openroad script /openlane/scripts/openroad/droute.tcl
[ERROR]: Log: ../home/AIC/Caravel_Integration/openlane/user_proj_example/runs/23_03_31_19_53/logs/routing/17-detailed.log
[ERROR]: Last 10 lines:
[INFO DRT-0186] Done with 294 vertical wires in 9 frboxes and 726 horizontal wires in 6 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 00:01:10, elapsed time = 00:00:38, memory = 1691.01 (MB), peak = 2435.92 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1691.01 (MB), peak = 2435.92 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:26, memory = 2698.28 (MB).
child killed: kill signal
[ERROR]: Creating issue reproducible...

I also get the following lines. Any solution?

[ERROR]: Flow failed.
make[1]: *** [Makefile:73: user_proj_example] Error 255
make[1]: Leaving directory '/home/AIC/Caravel_Integration/openlane'
make: *** [Makefile:107: user_proj_example] Error 2

Hello everyone, I have a question regarding the use of the logic analyzer. Is it possible to drive a logic analyzer output port and at the same time use it as an input port? Do I need to add a tristate before connecting to the output port?

Hi! Currently working on a mixed signal design in Caravel. I was wondering how to add the analog modules. Can the LEF, GDS, Verilog behavioural files for the analog modules be put in the config.json file for the user_project wrapper under extra LEF, GDS, and Verilog blackbox files? Or is it supposed to be done in a different way? Thanks in advance!

Hi! I would like to know the specs of the RISC-V processor in the caravel. https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/#processor It's mentioned that the processor core is based on a VexRiscv minimal+debug configuration. What does that mean? Also what is the pipeline stage depth? Thanks in advance!

While synthesizing caravel_user_project ,Wire user_proj_example.\wbs_dat_o is used but has no driver for example project itself

Could someone point me to detailed documentation on the logic analyzer? Aside from the wrapper verilog and a couple notes online I can't find anything after a lot of hunting. Certainly there's some specific documentation on the interface description for this and the wishbone bus?

anyone know how to start openroad gui from the context of a failed caravel build?

We have a core of only macros on our User_project_wrapper top-level. In order to try and resolve the slew warnings for our top level clock signals that have high fanouts we wanted to turn on clock tree synthesis. When attempting to do this we get LVS errors that show the new cells added to the top level are not connected to power. The LVS errors also show up whenever we try to run any configuration that seems to add cells to the top level ie. diode insertion, buffer insertion, design optimization. We do have synth_elaborate_only on, but assumed that would only affect the synthesis step of the flow. Does this behavior make sense at all?

Hello everyone, I want to know if this is correct, in my Core module I had multiple sub-modules, when I fill in the "FP_PDN_MACRO_HOOKS" I usually use the power pin connection" vccd1 vssd1 vccd1 vssd1". Usually that generates some LVS errors because some sub-modules are not connected to those pins, so I go to OpenROAD -GUI and just choose the power grid that passes over the module. e.g. the "6__7_" module is connected to vccd1, and vssd1. but as u can see in the picture the power pin cannot be connected to the module "7__6_" so I used power pins vdda1 and vssa1. My questions are: that is a correct connection? that could generate some error? How can I uses only vccd1 and vssd1?

Why don't any gates show up in GDS for my simple user_proj_example? Any ideas why that may be? It's not quite the same example project but hardly anything has changed. Flow succeeds at all stages, but GDS for the caravel harness shows all the gates, but not my macros.

@Tim Edwards is there an analog version of the gf180mcu caravel?

I'm a little stuck on this section of the caravel installation instructions

cd <project_name> # project_name is the name of your repo

mkdir dependencies

export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src # you need to export this whenever you start a new shell

export PDK_ROOT=$(pwd)/dependencies/pdks # you need to export this whenever you start a new shell

# export the PDK variant depending on your shuttle, if you don't know leave it to the default

# for sky130 MPW shuttles....
export PDK=sky130A

# for the gf180 GFMPW shuttles...
export PDK=gf180mcuC



make setup

I tried to follow this but I don't have

volare

and the installation doesn't seem to be working for me.

tom@tom-desktop:~/repos/projects/caravel_user_project$ sudo apt-get install python3 python3-pip xz-utils
[sudo] password for tom: 
Reading package lists... Done
Building dependency tree... Done
Reading state information... Done
python3 is already the newest version (3.10.6-1).
python3-pip is already the newest version (22.2+dfsg-1ubuntu0.2).
xz-utils is already the newest version (5.2.5-2.1).
xz-utils set to manually installed.
0 upgraded, 0 newly installed, 0 to remove and 200 not upgraded.
tom@tom-desktop:~/repos/projects/caravel_user_project$ python3 -m pip install --upgrade --no-cache-dir volare
Defaulting to user installation because normal site-packages is not writeable
Requirement already satisfied: volare in /home/tom/.local/lib/python3.10/site-packages (0.7.3)
Requirement already satisfied: requests<3,>=2.27.0 in /home/tom/.local/lib/python3.10/site-packages (from volare) (2.31.0)
Requirement already satisfied: rich<13,>=12 in /home/tom/.local/lib/python3.10/site-packages (from volare) (12.6.0)
Requirement already satisfied: pcpp<2,>=1.2 in /home/tom/.local/lib/python3.10/site-packages (from volare) (1.30)
Requirement already satisfied: click<9,>=8.0.0 in /usr/lib/python3/dist-packages (from volare) (8.0.3)
Requirement already satisfied: pyyaml<7,>=5 in /usr/lib/python3/dist-packages (from volare) (5.4.1)
Requirement already satisfied: certifi>=2017.4.17 in /home/tom/.local/lib/python3.10/site-packages (from requests<3,>=2.27.0->volare) (2023.5.7)
Requirement already satisfied: urllib3<3,>=1.21.1 in /usr/lib/python3/dist-packages (from requests<3,>=2.27.0->volare) (1.26.9)
Requirement already satisfied: charset-normalizer<4,>=2 in /home/tom/.local/lib/python3.10/site-packages (from requests<3,>=2.27.0->volare) (3.1.0)
Requirement already satisfied: idna<4,>=2.5 in /home/tom/.local/lib/python3.10/site-packages (from requests<3,>=2.27.0->volare) (3.4)
Requirement already satisfied: pygments<3.0.0,>=2.6.0 in /home/tom/.local/lib/python3.10/site-packages (from rich<13,>=12->volare) (2.15.1)
Requirement already satisfied: commonmark<0.10.0,>=0.9.0 in /home/tom/.local/lib/python3.10/site-packages (from rich<13,>=12->volare) (0.9.1)
tom@tom-desktop:~/repos/projects/caravel_user_project$ volare --version
volare: command not found

In any event, as @Tim Edwards said since I have already installed the PDK I shouldn't need volare anyway but my understanding is that caravel's

make setup

also installs caravel lite and the management core so how to I do that without having to install

volare

? can I just...

export OPENLANE_ROOT=/home/tom/repos/edatools/Openlane
export PDK_ROOT=/home/tom/repos/edalibs/pdks/gf180mcu
export PDK=gf180mcuC

followed by make setup?

is there a reason why the dv simulation in caravel_user_project doesn't respect user_defines.v?

Are the caravel analog pins output only? or in and out?

inout [MPRJ_IO_PADS-10:0] analog_io

Does anyone know a tool that can read in a waveform (like gtkwave) and check busses for standard compliance, like e.g. wishbone bus for Caravel?

How can I start the openroad gui for analyzing congestions from a Caravel User Project?

hello , I was trying to use Caravel template to start using OpenLane but, when i try to run the example project I got this, Does anyone know how to solve this issue?

Hi, could you help me, plz! While hardening my design, Im getting stuck in the step number 30 as shown: Is it normal that it might take too long !?

Validating Caravel SoC + User Project Design on FPGA: https://github.com/bol-edu/caravel-soc_fpga https://lu.ma/v37ub54h