https://github.com/efabless/caravel/blob/main/openlane/gpio_control_block/yosys_mapping.v hi all, i was curious - what is the purpose of this file. i was also trying to understand what is $__DFFSR__ i was looking to sky130 - if i could find it -> found nothing similar. also is it like some kind of variable -> if so, where is it set & what stage?

Is it possible to use caravel_user_project without Docker? I want to use my PowerPC server but Docker doesn't run on PPC.

👋 Hello, team! After clone my caravel_user_project repo I run make setup and I'm getting this errors: make[2]: Entering directory '/home/pablo/asic/openlane_scr' Makefile26 warning: undefined variable 'DOCKER_MEMORY' Makefile42 warning: undefined variable 'ROUTING_CORES' Makefile84 warning: undefined variable 'STD_CELL_LIBRARY' permission denied while trying to connect to the Docker daemon socket at unix///var/run/docker.sock Post "http://%2Fvar%2Frun%2Fdocker.sock/v1.24/images/create?fromImage=efabless%2Fopenlane&tag=2023.07.19": dial unix /var/run/docker.sock: connect: permission denied make[2]: * [Makefile115 pull-openlane] Error 1 make[2]: Leaving directory '/home/pablo/asic/openlane_scr' make[1]: * [Makefile90 openlane] Error 2 make[1]: Leaving directory '/home/pablo/Documents/Allegro/efabless/GITHUB/caravel_user_project_TEST/openlane' make: * [Makefile202 openlane] Error 2 Can somebody help me with this?

Hi! I have a question regarding the programming of the instruction memory used by the PicoRV32, we are trying to run the SoC on a ZedBoard FPGA for testing purposes since we also have our own added user components. We are using a wishbone bus for bus communication. I believe that memory is located not on the PicoRV32 but on the SoC in the SRAM, is there a way to program the SRAM through the ZedBoard's ARM processor (which is an AXI bus protocol) or to flash the SRAM using the QSPI flash interface? I have looked at the caravel_board and from what I am understanding, the way it programs the caravel processor is by flashing the caravel processor through SPI flash.

Hello, I'm using the caravel user project and I've completed the design. However, I am struggling with using "make verify" and I'm not sure if it's necessary. As far as I understand it's only for simulation purposes. I have already implemented the design and performed sdf-annotated post-implementation simulation and the design is working as expected. Is there any additional benefit from using the make verify command?

Hello! Does anyone know why I might have LVS errors in precheck? I attach the LVS precheck log and the user project wrapper configuration file.

hi is the GPIO pins 14 to 24 dedicated only for digital...or can we use this for analog also. one more thing what is the voltage range for analog that we can give through GPIO other than other than 3.3v and 1.8v .

@jeffdi @Tim Edwards Can it be, that in pad

sky130_ef_io_gpiov2_pad_wrapped

the wire

PAD_A_NOESD_H

is not properly connected to the pad? This pad connection is also exposed in the analog caravel (as

gpio_noesd

). Without proper documentation of the pad (which I don’t find) and without the nestlist of the pad (which I don’t have) it is impossible to confirm, but looking at the magic file there seems to be a small gap (see screenshots). Can someone from efabless please confirm?

hello, i am violating setup when concatenating my design into user_project_wrapper. i tried reducing the frequency 10 times but the setup slack didn't change at all. Can someone help me?

Hi @Tim Edwards @Matt Venn Is it possible to program and control LA pins in management area using SPI ?For example I want to send a PWM encoded code via SPI which needs to be applied at LA pins with variable duty cycle

Approx how many clocks can we expect this update to happen for LA pins?

@samarth jain: No, the LA pins cannot be accessed from the housekeeping SPI. You could, however, use housekeeping to drive a GPIO value and read that into the user project area. I assume that you wanted to do it internally to the chip, though, and not take up extra GPIOs.

@Tim Edwards I have made a potentiometer dac with 6 bits control and I had connected that 6 bits to LA pins,how can I control the output of dac then ? If house keeping SPI can’t access the LA.what protocol available can be used for this application?I need to change the 6 bit values to make a ramp voltage from dac

Hi everyone, is there any technical documentation for the spec of the caravel GPIOs pads? We are assuming they are all level shifted up to 3.3v, is that correct? It would be nice for the future to simultaneously have 1.8v and 3.3v pads. It looks like the pad itself is capable of doing this from the skywater spice model, is this true? Is there a spec on the output (how many miliamps it can drive etc)?

hi, when i appended the macro to user_project_wapper, i got a hold and setup violation during signoff. I tried checking the sta summary in placement and routing and the sta was quite good. But when it comes to the signoff process, it's very bad. 1, I want to ask what the signoff process actually did. 2, Can you suggest me ways to fix errors in that process? 3, Not sure if it's true. I think it's possible that the power and ground pins pass through my macro (in blue, mprj macro image), leading to an error during the signoff process. So how do I put those pins on one edge of the wrapper?

So @Tim Edwards @Mitch Bailey does this mean registers of housekeeping registers and gpio are shared? and they can be written directly?

@jeffdi @Mitch Bailey @Tim Edwards Sorry for interrupting your Sunday, but I need urgent help! I am failing the “consistency” check in mpw-precheck for an analog project using caravan, and I have no idea what it does exactly, nor how to fix it. I can’t find a log file or anything that gives me an idea. Please help, TO is scheduled tomorrow

Hi all, I am currently trying to understand the power-on configurations for GPIO in

user_defines.v

. Taking a look at the individual bit fields for the GPIO pad control:

#define MGMT_ENABLE	  0x001
#define OE_OVERRIDE	  0x002
#define INPUT_ENABLE	  0x004
#define OUTPUT_ENABLE	  0x008
#define SCHMITT_SELECT	  0x010
#define SLEW_SELECT	  0x020
#define PULLUP_SELECT	  0x040
#define PULLDOWN_SELECT	  0x080
#define DRIVE_SELECT_MASK 0x300

This means that all of the following user configurations basically ignore the

io_oeb

signal from

user_project_wrapper

, right?

GPIO_MODE_USER_STD_INPUT_*
GPIO_MODE_USER_STD_OUTPUT

For

GPIO_MODE_USER_STD_BIDIRECTIONAL

the

OE_OVERRIDE

bit is not set, therefore

io_oeb

is used. It only has the

OUTPUT_ENABLE

bit set, but shouldn't the

INPUT_ENABLE

bit also be set?

Hello, I have successfully merged my macro into user_project_wrapper. However, after the flow completed, I noticed my 2.syn_sta_summary setup violation. I think the real error in config.json is because I set it wrong or forgot to set a certain variable. Please help me.

Hi there, I have been trying to push my synthesized files into efabless git server. Our team's design files are quite large (total >2GB) so I need to use Git LFS; but while pushing normal code to server works well, the

git push

for Git LFS files just did not work. Note that I can still push Git LFS files into Github. I would really appreciate help to fix this problem. Thanks!

@Mitch Bailey @Tim Edwards can GPIO pads be used as analog inout if I connect them to user area?I wanted pads to give voltage reference

I see there is io_out,io_in and analog_io. Are these all connected to a single pad? @Mitch Bailey

Yes, but the indices are offset. From

verilog/rtl/user_project_wrapper.v

// Analog (direct connection to GPIO pad---use with caution)
    // Note that analog I/O is not available on the 7 lowest-numbered
    // GPIO pads, and so the analog_io indexing is offset from the
    // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
    inout [`MPRJ_IO_PADS-10:0] analog_io,

So

analog_io[0]

,

io_out[7]

,

io_in[7]

all connect to the same gpio.

@Mitch Bailey @Tim Edwards @Matt Venn I seeflash csb,flash clk ,flash io1 and flash io0? can we use flash with the caravel?I mean is there a flash controller already inbuilt which we can control using program in mcu?

@Mitch Bailey How the analog_io* are mapped to io_in*, io_out* and io_oeb* there are 29 analog_io 0:28 and the others io_*0:37 Can i use the remaining io29:37 for other design usage? like giving 1.8 V voltage references to fet gates?

@Tim Edwards @Mitch Bailey Do we have any information about the GF180MCU MPW board design pinout?

Hi, how do we run the openLane flow for the caravel SoC. what are the variables we need to set for running the OpenLane? if any tutorial please do share. thanks bharath

Hi, I found an issue with running dv for gfmpw-1 shuttle. When running longer tests, caravel sets the wb_rst_i input signal to undefined state (and all other singals follow later). It happens at constant time of 32000 clock cylces. It doesn't change with delaying of setting I/O pins, but I found it only changes when .c file program length changes - looks like it dependent only on caravel. I can reproduce it even on provided user_proj_example with only I/O output and input clock from wb pins. Have anyone else encountered this issue? Or maybe someone had success with dv testing on gfmpw-1?

@John Myers has left the channel

I have a macro available. I want to incorporate that macro into my design. I created my design macro. Then combine that design macro into user_project_wrapper. So what do I need to do to complete my idea? I tried incorporating macros into my design but I don't know how to properly configure the config.json file. Can someone help me? Please