Hi I am trying to run openram and I get the error regarding open-source-silicon.dev #openram

Hi , I am trying to run openram and I get the erro...

Mihai Hurdugaciu

02/06/2023, 2:56 PM

Hi , I am trying to run openram and I get the error regarding ngspice files from PDK .

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$ python3 sram_compiler.py macros/test1.py 
Traceback (most recent call last):
  File "/home/mihaih/OpenRAM/sram_compiler.py", line 49, in <module>
    openram.init_openram(config_file=args[0])
  File "/home/mihaih/OpenRAM/compiler/globals.py", line 199, in init_openram
    import_tech()
  File "/home/mihaih/OpenRAM/compiler/globals.py", line 572, in import_tech
    tech_mod = __import__(OPTS.tech_name)
  File "/home/mihaih/OpenRAM/technology/sky130/__init__.py", line 32, in <module>
    raise SystemError("Did not find {} under {}".format(sky130_lib_ngspice, open_pdks))
SystemError: Did not find /home/mihaih/OpenRAM/sky130A/sky130A/libs.tech/ngspice/sky130.lib.spice under /home/mihaih/OpenRAM/sky130A/sky130A/libs.tech

Where do I need to setup the PDK_ROOT? After Openram setup I have several places were I have Sky130 pdk :

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├── open_pdks
│   ├── common
│   ├── runtime
│   ├── scripts
│   ├── sky130
│   └── sources
├── openram.egg-info
├── sky130A
│   ├── libs.ref
│   └── libs.tech
├── sky130B
│   ├── libs.ref
│   └── libs.tech
├── sky130_fd_bd_sram
│   ├── cells
│   └── docs
├── skywater-pdk
│   ├── docs
│   ├── libraries
│   ├── scripts
│   └── third_party
└── technology
    ├── freepdk45
    ├── scn3me_subm
    ├── scn4m_subm
    ├── setup_scripts
    └── sky130

thanks

Matthew Guthaus

02/06/2023, 5:26 PM

I suggest running using our Makefile which uses docker (and soon conda) so that you get all the right environment, PDK version and tool versions. There are some issues if you don't use correct versions.

Mihai Hurdugaciu

02/06/2023, 7:55 PM

OK, Meanwhile I tried

$PDK_ROOT = #HOME/OpenRAM

seems to work. I manage to run a config and I have the error from the picture

RROR: file bitcell_base.py: line 273: Must override build_graph function in bitcell base class.

but I see generated files . • next I use the sram module in a hierarchical OpenLane flow design (SRAM is the only hardened macro) and I get this DRCs :

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Magic DRC Summary:
Source: /openlane/designs/vsdmemsoc/runs/RUN_CUSTRAM/reports/signoff/drc.rpt
Violation Message "This layer can't abut or partially overlap between subcells "found 7198 Times.
Violation Message "Metal3 > 3um spacing to unrelated m3 < 0.4um (met3.3d) "found 30 Times.
Violation Message "Can't overlap those layers "found 623746 Times.
Violation Message "Min area of metal1 holes > 0.14um^2 (met1.7) "found 447689 Times.
Violation Message "All nwells must contain metal-connected N+ taps (nwell.4) "found 1280 Times.
Total Magic DRC violations is 1079943

Do you have any idea for possible sources for the violations ? I expect that I do not need to manually correct all of them in magic.

test1.py

Matthew Guthaus

02/06/2023, 10:52 PM

You must be using an outdated version of openram... That was a bug that was fixed.

Matthew Guthaus

02/06/2023, 10:52 PM

(It's not really an error)

Matthew Guthaus

02/06/2023, 10:53 PM

OpenLane cannot run DRC on OpenRAM macros because we use "core memory" design rules that don't pass user design rules.

Matthew Guthaus

02/06/2023, 10:53 PM

You can use klayout instead.

Mihai Hurdugaciu

02/07/2023, 4:18 AM

OK, I will ignore the errors. Thank you. I use v1.2.1 is this old?

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|==============================================================================|
|=========                       OpenRAM v1.2.1                       =========|
|=========                                                            =========|
|=========               VLSI Design and Automation Lab               =========|
|=========        Computer Science and Engineering Department         =========|
|=========            University of California Santa Cruz             =========|
|=========                                                            =========|

Matthew Guthaus

02/07/2023, 3:00 PM

That is the most recent, so I'm not sure why you are still getting those errors. Can you share your config file?

Mihai Hurdugaciu

02/07/2023, 3:02 PM

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DESIGN_NAME": "vsdmemsoc",
    "VERILOG_INCLUDE_DIRS": "dir::src/include",
    "VERILOG_FILES": "dir::src/module/*.v",
    "EXTRA_LEFS":     "dir::src/macros/hdp_sky130_sram_1kbytes_1rw1r_32x256_8.lef",
    "EXTRA_GDS_FILES": "dir::src/macros/hdp_sky130_sram_1kbytes_1rw1r_32x256_8.gds",
    "EXTRA_LIBS":      "dir::src/macros/hdp_sky130_sram_1kbytes_1rw1r_32x256_8_TT_1p8V_25C.lib",

    "CLOCK_PORT": "CLK",
    "CLOCK_PERIOD": 10,

    "VDD_NETS": "vccd1",
    "GND_NETS": "vssd1",

    "FP_SIZING": "relative",
    "PL_TARGET_DENSITY": 0.2,
    "RT_MAX_LAYER": "met5",


    "FP_PDN_MACRO_HOOKS": "mem vccd1 vssd1 vccd1 vssd1, cntrl vccd1 vssd1 vccd1 vssd1",

    "BASE_SDC_FILE": "dir::src/sdc/vsdmemsoc_synth.sdc",
    "SYNTH_SIZING": 1,
    "SYNTH_FLAT_TOP": 1,
    "SYNTH_STRATEGY": "AREA 0",
    "FP_CORE_UTIL" : 15,
    "PL_MACRO_HALO": "100 100",

    "ROUTING_CORES": 6,

    "MAGIC_DRC_USE_GDS": false,
    "QUIT_ON_MAGIC_DRC": false,
    "RUN_KLAYOUT_XOR": false,
    "RUN_KLAYOUT_DRC" : true,
    "DESIGN_IS_CORE": true

Matthew Guthaus

02/07/2023, 3:23 PM

I mean your openram config.

Mihai Hurdugaciu

02/07/2023, 3:24 PM

Ok, It is attached in previews messages :

test1.py

Matthew Guthaus

02/07/2023, 3:35 PM

The copyright is a bit suspect since it is based on my BSD config files 🙂

Matthew Guthaus

02/07/2023, 3:36 PM

You can just use the pre-made macro which is exactly this config https://github.com/VLSIDA/sky130_sram_macros/tree/dev/sky130_sram_1kbyte_1rw1r_32x256_8

Mihai Hurdugaciu

02/10/2023, 2:32 PM

ok, Thank you.

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