Hi I am trying to run openram and I get the error regarding

Question

Hi I am trying to run openram and I get the error regarding ngspice files from PDK ```$ python3 sram compiler py macros test1 py Traceback most recent call last File home mihaih OpenRAM sram compiler py line 49 in lt module gt openram init openram config file=args 0 File home mihaih OpenRAM compiler globals py line 199 in init openram import tech File home mihaih OpenRAM compiler globals py line 572 in import tech tech mod = import OPTS tech name File home mihaih OpenRAM technology sky130 init py line 32 in lt module gt raise SystemError Did not find under format sky130 lib ngspice open pdks SystemError Did not find home mihaih OpenRAM sky130A sky130A libs tech ngspice sky130 lib spice under home mihaih OpenRAM sky130A sky130A libs tech``` Where do I need to setup the PDK ROOT After Openram setup I have several places were I have Sky130 pdk ``` open pdks common runtime scripts sky130 sources openram egg info sky130A libs ref libs tech sky130B libs ref libs tech sky130 fd bd sram cells docs skywater pdk docs libraries scripts third party technology freepdk45 scn3me subm scn4m subm setup scripts sky130``` thanks

Matthew Guthaus · Answer

I suggest running using our Makefile which uses docker and soon conda so that you get all the right environment PDK version and tool versions There are some issues if you don t use correct versions

Mihai Hurdugaciu · Answer

OK Meanwhile I tried `$PDK ROOT = HOME OpenRAM` seems to work I manage to run a config and I have the error from the picture `RROR file bitcell base py line 273 Must override build graph function in bitcell base class ` but I see generated files next I use the sram module in a hierarchical OpenLane flow design SRAM is the only hardened macro and I get this DRCs ```Magic DRC Summary Source openlane designs vsdmemsoc runs RUN CUSTRAM reports signoff drc rpt Violation Message This layer can t abut or partially overlap between subcells found 7198 Times Violation Message Metal3 gt 3um spacing to unrelated m3 lt 0 4um met3 3d found 30 Times Violation Message Can t overlap those layers found 623746 Times Violation Message Min area of metal1 holes gt 0 14um^2 met1 7 found 447689 Times Violation Message All nwells must contain metal connected N+ taps nwell 4 found 1280 Times Total Magic DRC violations is 1079943``` Do you have any idea for possible sources for the violations I expect that I do not need to manually correct all of them in magic

Matthew Guthaus · Answer

You must be using an outdated version of openram That was a bug that was fixed

Matthew Guthaus · Answer

It s not really an error

Matthew Guthaus · Answer

OpenLane cannot run DRC on OpenRAM macros because we use core memory design rules that don t pass user design rules

Matthew Guthaus · Answer

You can use klayout instead

Mihai Hurdugaciu · Answer

OK I will ignore the errors Thank you I use v1 2 1 is this old ```|==============================================================================| |========= OpenRAM v1 2 1 =========| |========= =========| |========= VLSI Design and Automation Lab =========| |========= Computer Science and Engineering Department =========| |========= University of California Santa Cruz =========| |========= =========|```

Matthew Guthaus · Answer

That is the most recent so I m not sure why you are still getting those errors Can you share your config file

Mihai Hurdugaciu · Answer

```DESIGN NAME vsdmemsoc VERILOG INCLUDE DIRS dir src include VERILOG FILES dir src module v EXTRA LEFS dir src macros hdp sky130 sram 1kbytes 1rw1r 32x256 8 lef EXTRA GDS FILES dir src macros hdp sky130 sram 1kbytes 1rw1r 32x256 8 gds EXTRA LIBS dir src macros hdp sky130 sram 1kbytes 1rw1r 32x256 8 TT 1p8V 25C lib CLOCK PORT CLK CLOCK PERIOD 10 VDD NETS vccd1 GND NETS vssd1 FP SIZING relative PL TARGET DENSITY 0 2 RT MAX LAYER met5 FP PDN MACRO HOOKS mem vccd1 vssd1 vccd1 vssd1 cntrl vccd1 vssd1 vccd1 vssd1 BASE SDC FILE dir src sdc vsdmemsoc synth sdc SYNTH SIZING 1 SYNTH FLAT TOP 1 SYNTH STRATEGY AREA 0 FP CORE UTIL 15 PL MACRO HALO 100 100 ROUTING CORES 6 MAGIC DRC USE GDS false QUIT ON MAGIC DRC false RUN KLAYOUT XOR false RUN KLAYOUT DRC true DESIGN IS CORE true```

Matthew Guthaus · Answer

I mean your openram config

Mihai Hurdugaciu · Answer

Ok It is attached in previews messages `test1 py`

Matthew Guthaus · Answer

The copyright is a bit suspect since it is based on my BSD config files slightly smiling face

Matthew Guthaus · Answer

You can just use the pre made macro which is exactly this config <https github com VLSIDA sky130 sram macros tree dev sky130 sram 1kbyte 1rw1r 32x256 8>

Mihai Hurdugaciu · Answer

ok Thank you