if I wanted to custom tweak a few wires, where would roughly be the place to look? For example in openlane you can easily modify the DEF file that is passed around between stages as sort of a checkpoint to achieve this, is there any similar checkpoint mechanism with openram, or even what would be the least painful/destructive way to go about doing this, like some point or script where I can change things or have my script make a few changes and then let the flow go on as normal Am looking to decouple some wires and expose them as ports so I can individually control them Just started on this so looking for pointers so it's not as time consuming combing through the entire codebase

Hi , I am trying to run openram and I get the error regarding ngspice files from PDK .

$ python3 sram_compiler.py macros/test1.py 
Traceback (most recent call last):
  File "/home/mihaih/OpenRAM/sram_compiler.py", line 49, in <module>
    openram.init_openram(config_file=args[0])
  File "/home/mihaih/OpenRAM/compiler/globals.py", line 199, in init_openram
    import_tech()
  File "/home/mihaih/OpenRAM/compiler/globals.py", line 572, in import_tech
    tech_mod = __import__(OPTS.tech_name)
  File "/home/mihaih/OpenRAM/technology/sky130/__init__.py", line 32, in <module>
    raise SystemError("Did not find {} under {}".format(sky130_lib_ngspice, open_pdks))
SystemError: Did not find /home/mihaih/OpenRAM/sky130A/sky130A/libs.tech/ngspice/sky130.lib.spice under /home/mihaih/OpenRAM/sky130A/sky130A/libs.tech

Where do I need to setup the PDK_ROOT? After Openram setup I have several places were I have Sky130 pdk :

├── open_pdks
│   ├── common
│   ├── runtime
│   ├── scripts
│   ├── sky130
│   └── sources
├── openram.egg-info
├── sky130A
│   ├── libs.ref
│   └── libs.tech
├── sky130B
│   ├── libs.ref
│   └── libs.tech
├── sky130_fd_bd_sram
│   ├── cells
│   └── docs
├── skywater-pdk
│   ├── docs
│   ├── libraries
│   ├── scripts
│   └── third_party
└── technology
    ├── freepdk45
    ├── scn3me_subm
    ├── scn4m_subm
    ├── setup_scripts
    └── sky130

thanks

I am getting LVS errors when trying to build sky130_sram_1rw_tiny right out of the box; sequence of commands is git clone -> cd into openram folder -> set env vars -> make pdk -> make install -> cd into macros -> make sky130_sram_1rw_tiny Am I doing something wrong? Both stable and dev branches give me the same result ...

Hello All, I created a 16*3 memory macro in OpenRAM using sky130 technology . I am trying to verify the functionality of the same by simulating a spice file generated by OpenRAM itself . But the values seems to be not matching (pics are attached) . What could be the possible reason? I am using ngspice for simulation. The spice.rc file has these commands : set ngbehavior=hsa set ng_nomodcheck option noinit .

@Brady Etz has left the channel

@Matthew Guthaus: What sort of automatic documentation generation is OpenRAM currently capable of?

How to do parasitic extraction of gds files of OpenRAM memory macros (based on sky130)in magic? Is there any documentation?

Hi all. I wanted to know is there a possibility of generating Register Files or High Density or Low Density macros in OpenRAM. Thanks

Also what is the maximum size of Read/Write port for Dual Port macros?

Hi all I am using openram and built a example macro on sky130 pdk. I noticed that the power estimate values in the .html file is quite large. Is there a way to generate a more realistic power estimate? Thanks

Hi all. I am running openram and am facing the warning: "WARNING: file supply_tree_router.py: line 178: Unblocking supply self blockages to improve access (may cause DRC errors): vdd" and after that it writes annotated router gds file and then openram exits with no explicit error message. What could be the reason for this behavior. The log file is attached within.

My config file is attached with the message

I have tried building some of the other macros which work fine. Is this problem due to larger I/O size or is the system running out of memory etc.

FOR IMMEDIATE RELEASE OpenRAM Acquired by Private Company, to Become Closed-Source April 1, 2023 - In a surprising move, OpenRAM, the popular open-source memory compiler tool, has been acquired by a private company and will soon become a closed-source product. OpenRAM has been widely used in the semiconductor industry, with its open-source nature allowing for greater collaboration and innovation among users. However, the recent acquisition by a private company has caused concern among the open-source community, as the product's code will no longer be accessible to the public. The new owners of OpenRAM have announced that they will be developing a closed-source version of the software, which will be made available to customers for a fee. The company has cited the need for greater control over the product's development and the desire to monetize the tool as reasons for the decision to move away from open-source. This news has been met with disappointment by many members of the open-source community, who have long relied on OpenRAM for their memory design needs. Some have expressed concern that the move to closed-source will limit innovation and slow progress in the industry, as the community will no longer be able to freely collaborate on the tool's development. Despite these concerns, the new owners of OpenRAM have expressed their commitment to providing a high-quality product and continuing to serve the needs of their customers. They have also stated that they will be working to build strong relationships with the semiconductor industry and investing in the continued development of the tool. The new closed-source version of OpenRAM is set to be released in the coming months. In the meantime, the current open-source version will still be available to the public, but will no longer receive updates or support from the new owners. About OpenRAM: OpenRAM is a popular open-source memory compiler tool used in the semiconductor industry. It was originally developed by researchers at the VLSI CAD Laboratory at the University of California, Santa Cruz, and has been widely adopted by designers and engineers for its flexibility and ease of use. Contact: For more information, please contact the new owners of OpenRAM at info@closedsourceopenram.com.

Hi, when i tried to harden a 32x512 1rw sky130 sram macro , i encountered this problem and i don't know what can i do, any help will be appriciated.

ERROR: file sky130_replica_column.py: line 51: Replica bit cannot be the dummy row.

@Matthew Guthaus @Tim Edwards I still see only 1KB & 2KB SRAM are available for MPW tapeout.

sky130_sram_1kbyte_1rw1r_32x256_8.lef  sky130_sram_1kbyte_1rw1r_8x1024_8.lef  sky130_sram_2kbyte_1rw1r_32x512_8.lef  sram_1rw1r_32_256_8_sky130.lef

Is there is plan to add additional SRAM hardmacro into pdk in mpw tape-out?

@Matthew Guthaus I'm going to be doing some xray imaging of MPW1 chips

would it be useful to take some measurements from openram?

Anything in particular you want measured @Matthew Guthaus?

Hi everyone Can someone help with this error? Where to get this file? -

sky130_sram_2kbyte_1rw1r_32x512_8.v

Thanks in advance!

hello everyone i need a help for my schematic design of 6T SRAM cell. for simulation how to initialize the value for Q Qbar in EDA tools (Sky130 efabless)

is there any one who can also help me with anykind of manual for xschem in sky130 ?

@Matthew Guthaus I’m looking at the

openram_sense_amp

schematic.

.SUBCKT sky130_fd_bd_sram__openram_sense_amp BL BR DOUT EN VDD GND
X1000 GND EN a_56_432# GND sky130_fd_pr__nfet_01v8 W=0.65 L=0.15 m=1
X1001 a_56_432# dint_bar dint GND sky130_fd_pr__nfet_01v8 W=0.65 L=0.15 m=1
X1002 dint_bar dint a_56_432# GND sky130_fd_pr__nfet_01v8 W=0.65 L=0.15 m=1

X1003 VDD dint_bar dint VDD sky130_fd_pr__pfet_01v8 W=1.26 L=0.15 m=1
X1004 dint_bar dint VDD VDD sky130_fd_pr__pfet_01v8 W=1.26 L=0.15 m=1

X1005 BL EN dint VDD sky130_fd_pr__pfet_01v8 W=2 L=0.15 m=1
X1006 dint_bar EN BR VDD sky130_fd_pr__pfet_01v8 W=2 L=0.15 m=1

X1007 VDD dint_bar DOUT VDD sky130_fd_pr__pfet_01v8 W=1.26 L=0.15 m=1
X1008 DOUT dint_bar GND GND sky130_fd_pr__nfet_01v8 W=0.65 L=0.15 m=1

.ENDS sky130_fd_bd_sram__openram_sense_amp

When

EN

is low, I think all paths from

GND

to `dint`/`dint_bar` are cut-off. Won’t this result in indeterminate input to the

DOUT

inverter? Am I missing something?

Hi all, I am facing the following problem for all the single port memories that I am trying to generate with sky130 tech

ERROR: file sky130_replica_column.py: line 52: Replica bit cannot be the dummy row.

I have read a thread before regarding this problem. I suppose that is the same, because I am using the latest version of OpenRAM. Anyways, what should I do to generate a single port memory for sky130 tech?

Hello all , in the recent version of OpenRAM , i used the following configuration file (which worked for previous version) , for which I am getting the following error . I am not able to understand this error . "Replica bit cannot be the dummy row" What modification is needed for the configuration file??

@Jesse Cirimelli-Low @Matthew Guthaus When I am trying to generate an 8KB Memory using , I am getting the following Warnings and process is killed.Attached is the log file

what would make an SRAM not work post tapeout? if it's too big could we predict that it wouldn't work with spice sims ? are there any data available from the sky130 post tapeout tests that might show why some macros didn't work??

does openram have spef files? if not how do we do STA with a design that includes it?