https://open-source-silicon.dev logo
Channels
aa
abcc
activity
adiabatonauts
analog-design
announce
announcements
b2aws
b2aws-tutorial
bag
basebands
beagleboard
bluetooth
board-respin
cadence-genus
cadence-innovus
cadence-spectre
cadence-virtuoso
caravan
caravel
caravel-board
chilechipmakers
chip-yard
chipignite
chipignite2206q_stanford_bringup
chisel
coalition-for-digital-environmental-sustainability
community_denmark_dtu
containers
courses
design-review
design-services
dffram
digital-design
digital-electronics-learners
discord-mods
dynamic-power-estimation
efabless
electric
events
fasoc
fault
foss-asic-tools
fossee-iitb-esim
fossee-iitb-google-sky130
fpga
funding
fuserisc
general
generative-ai-silicon-challenge
genius-vlsi
gf180
gf180mcu
hardware-beginners
help-
ieee-sscs-cac-23
ieee-sscs-dc-21q3
ieee-sscs-dc-22
ieee-sscs-dc-23
ihp-sg13g2
images
infiniband
j-core
japan-region
junk
klayout
latam_vlsi
layouteditor
lvs
lvs-analysis
magic
magical
maker-projects
maker-zone
microwatt
mpw-2-silicon
mpw-one-clean-short
mpw-one-silicon
neuro-mem
nydesign
open_pdks
open-pdk
openadiabaticlogic
openfpga
openhighqualityresonators
openlane
openlane_cloudrunner
openlane-development
openocd
openpositarithmetic
openpower
openram
openroad
opentitan
osu
pa-test-chip
paracells
pd-openlane-and-sky130
picosoc
pll
popy_neel
power
private-shuttle
rad-lab-silicon
radio
rdircd
reram
researchers
rf-mmw-design
rios
riscv
sdram
serdes
shuttle
shuttle-precheck
shuttle-status
silicon-photonics
silicon-validation
silicon-validation-private
sky130
sky130-ci
sky130-pv-workshop
sky65
sky90
skywater
sram
stdcelllib
strive
swerv
system-verilog-learners
tapeout-job
tapeout-pakistan
team-awesome
timing-closure
toysram
travis-ci
uvm-learners
vendor-synopsys
venn
verification-be
verification-fe
verilog-learners
vh2v
vhdl
vhdl-learners
vliw
vlsi_verilog_using_opensource_eda
vlsi_verilog_using_opensoure_eda
vlsi-learners-group
vlsi101
waveform-viewers
xls
xschem
xyce
zettascale
Powered by
Title
a

alex d

02/08/2023, 2:57 AM
I am getting LVS errors when trying to build sky130_sram_1rw_tiny right out of the box; sequence of commands is git clone -> cd into openram folder -> set env vars -> make pdk -> make install -> cd into macros -> make sky130_sram_1rw_tiny Am I doing something wrong? Both stable and dev branches give me the same result ...
m

Mitch Bailey

02/08/2023, 4:04 AM
@alex d Getting the openram macros to pass LVS with magic and netgen can be tricky because 1. some layout cells do not have bulk/well contacts 2. some layout cells have multiple unconnected power rails with the same text 3. netgen creates proxy pins for unmatched ports in otherwise matching circuits. This works if the ports are not connected, but may cause problems if the nets are merged at a higher hierarchy. There are work arounds for all of these issues. Can you post your gds and spice? I’ll take a look and may be able to suggest something.
a

alex d

02/08/2023, 4:23 AM
Here you go, and just to clarify, this is right out of the box with no modifications made of any sort (fresh repo clone running the sky130_sram_1rw_tiny example through docker). If it was failing after I made some changes to it I would understand that I messed something up and it would be on me, but LVS issues right out of the box seems odd
m

Matthew Guthaus

02/08/2023, 6:19 PM
@alex d I've found that it is very dependent on which version of Magic and netgen. There were many changes over a year or so that kept adding issues with the items @Mitch Bailey mentions. You are using the docker so that was the last known version to work for us.
I have never seen this magic warning before: [openram.verify.magic/run_lvs]: Warning: Equate pins: cell sky130_fd_pr__special_pfet_pass is a placeholder, treated as a black box. [openram.verify.magic/run_lvs]: Warning: Equate pins: cell sky130_fd_pr__special_pfet_pass is a placeholder, treated as a black box.
Looking through the mismatches, most of them are from must-connect supply pins that are later connected. In particular, it looks like the colend/colenda cells are not connected to vssd1/vccd1. This is likely an extraction issue.
a

alex d

02/08/2023, 7:03 PM
So I'm not doing anything "wrong" per se, right?
m

Matthew Guthaus

02/08/2023, 7:10 PM
No, nothing at all wrong.
(This has been my biggest frustration in the whole project, to be honest.)
m

Mitch Bailey

02/09/2023, 7:30 AM
I have never seen this magic warning before:
[openram.verify.magic/run_lvs]: Warning: Equate pins: cell sky130_fd_pr__special_pfet_pass is a placeholder, treated as a black box.
[openram.verify.magic/run_lvs]: Warning: Equate pins: cell sky130_fd_pr__special_pfet_pass is a placeholder, treated as a black box.
I believe all device models that are extracted as subcircuits have this message. It is not (generally) a problem.
(This has been my biggest frustration in the whole project, to be honest.)
I sort of chuckled when I read that. From the tool side, one of the biggest frustrations has been dealing with layout and schematics that only match at higher levels. Hopefully there’s some relatively simple solution.