Hello, Regarding g5v0d10v5 NMOS devices, which app...
# ieee-sscs-dc-22
a
Hello, Regarding g5v0d10v5 NMOS devices, which appear to be symmetrical in terms of drain and source, are there restrictions to the Gain-Drain voltage? If there is a 5V max for Vgs to prevent oxide degradation, we assume there is a 5V max for Vgd too. But also, we wonder if a negative voltage of sufficient magnitude could cause problems since we have Vgd = -10V when Vds=10V and Vgs=0. If this is the case, it seems like the 10.5V devices can't really reach that value since they are limited by Vgd max around 5V. Are there other devices with Vgs_max higher than 5V to overcome this? @Boris Murmann @Tim Edwards
@Pablo Vera
b
Can you provide a pointer to the documentation you are looing at?
b
I don't see an issue. The specs clearly tell you that for VGS=0, you can have VDS=10V, which also means VGD=-10V. This device is similar to a graded drain MOSFET, which can handle these conditions. There is no need to think about symmetry here because you are looking at an asymmetric condition. The source is the terminal with the lower voltage, i.e. it is electrically defined, not by how you label the node.
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j
Hello Boris, Thanks a lot for the reply. Sorry, but I'm still a bit confused with this. From my understanding, the gate voltage is limited by the maximum field over the oxide before it gets damaged, am I right? In this case, Vgd = -10v would imply a large field on the GD side of the oxide, even if it's reversed. How can this be explained?
b
Two things: 1) The transistor is off, so there is no channel underneath the gate oxide. This means the 10V do not drop across the gate oxide alone, but across a more complex cross section. 2) This is not a standard transistor. It has n-well surrounding the drain, which helps it deal with the large field. You can read up on graded drain transistors to understand this.
j
Thanks a lot, we'll take a look at the graded drain concept
What about the case in which we are just above the threshold voltage and we do have a channel?
b
That's a contradiction. You cannot have a channel with VGS just above Vt and VDS=10V. The channel is pinched off at the drain side.
j
I see, indeed, high Vds generates asymmetrical channel and pinched-off region... thanks!