One more question remaining from our presentation on friday (thanks for your patience) In the 3LFCC topology, we have seen that isolated NMOS power switch devices are quite essential for the performance we expect to achieve. We use the following devices for out NMOS swithes: sky130_fd_pr__nfet_g5v0d10v5 From the drawing in the documentation, it seems like the nfet_g5v0d10v5 devices are sitting in a deep N well (https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html#id44), does this mean that they can be isolated and we can connect body/bulk terminals to voltages different than ground? Can anyone help us to clarify this? Or to define which practices can allow us to obtain these isolated NMOS devices in the SKY130 technology? @Tim Edwards @Boris Murmann @Harald Pretl

Yes, any nMOS device can be placed inside a deep nwell layer, and will be isolated by the P region formed inside the deep nwell. The deep nwell has to be overlapped around the entire perimeter by an nwell, so it makes a very large structure, especially if you want to use it to set the back bias of a single transistor.

@Tim Edwards thanks for the reply I assume this passes LVS OK, or is there anything we need to take into account?

If you're doing it in magic, make sure you use

drc style drc(full)

to make sure you are capturing all of the DRC rule checks for deep nwell and high (3.3V) voltage.

ok! thanks!