yes it's renamed to GRT_OBS now

Hi, Could you please help me how I can create a block in Xschem by using this attached gate level Verilog file? Thanks.

Hello @Tim Edwards @jeffdi @Mitch Bailey, we are trying to do the online precheck on a version that tackles the FOM density error we get at tapeout. We tried several times but we get the attached message regarding the consistency check (it says it's not finding the analog wrapper within the caravel) and the job stops with an exception. We checked the gds file and it seems to be fine. The strange thing is that we re-submit the design we used before to pass the precheck and we get the same error. We can't find out the source of the error, your advice would be really appreciated. cc @Alfonso Cortés

11/4 Meet-Up Recording: https://us06web.zoom.us/rec/share/B8CK1-Vv178YCFHpLcc2xLzLMbyhvCygn4_WO9zy1VWsUMM1SwY6fe3J0mSBV4ub.bdmglDxYfmdvDBbc 11/11 Meet-Up Recording: https://us06web.zoom.us/rec/share/Z4pAPCaXB8lw2u-2_H87XcWtbj4jjWtj881J4tEu-OK6cdMWs83aKd1jJXUonMft.6BehzWOBACUd8naF 11/18 Meet-Up Recording: https://us06web.zoom.us/rec/share/I1uhDqTet_s0fRrSSvH4OVhxaYzAcm2phobeK3UGpzxD_B4lHE8ditSPETYNEUvC.6_uWzoXR8QGxgimu

Meet the Chipathletes article in SSCS magazine.

Hello @Mitch Bailey @Tim Edwards @jeffdi, we are still getting the consistency check SUBMODULE HOOKS fail during the precheck, even on a gds that was passing precheck before (details in my other post above). I'm concerned because a week has passed since we try to submit our design without success, not necessarily due to issues from our side, and at this pace we will miss the tapeout. We would really appreciate if you could help us, you can check our repo for Chiparthon project 6 in the link below (the latest precheck tag is "0570ed2d-2498-47c1-af9b-e83498bc1cc4"): https://platform.efabless.com/projects/1427

I’m going to attempt run the checks in https://github.com/d-m-bailey/extra_be_checks.git and post the results for each chip here. (I’ll stop if someone objects).

Chip-1 https://github.com/Ali-Sabir2/CHIP1_TAPEOUT.git

Chip-2 https://github.com/Mudassir-043/SSCS-PICO-CHIP-2.git

Chip-3 https://github.com/UAH-IC-Design-Team/sscs-22-project-wrapper.git

Chip-4 https://github.com/StephenKont/sscs_pico_chip_4.git

Chip-6 https://github.com/JorgeMarinN/3LFCC_AC3E_Tapeout.git

Sonia_Kiran has joined this channel by invitation from open-source-silicon.dev.

Chip-7 https://github.com/AndalibN/Electrochemical-Water-Quality-Monitoring.git

Chip-8 https://github.com/HALxmont/MixPix.git

Hello all, We finally managed to pass tapeout 🎉 But we would like to add some fixes and the tapeout process is taking 21 hours, is there any way to speed it up ?

Hello Everyone, Chip 3 - Austria, Brazil and USA1 - passed tapeout and is submitted. Thank you all for your help! Couldn’t have done it without the wonderful open sourced community here. This has been an incredible learning experience thanks to all of you and I’m extremely grateful.

@jeffdi, we are trying to run precheck and tapeout on Efabless (USA5/Chip7). A request has been submitted almost an hour ago but there's no progress. It wasn't taking so much time yesterday. How can we resolve this issue?

Hi everyone, We had a DRC clean online Precheck and we ran the Tapeout with it. The BEOL and FEOL errors were 65969 and 1143100 respectively. That seems like a lot of errors that didn't get caught in any earlier stages? @jeffdi @Mitch Bailey @Tim Edwards @Boris Murmann

I wrote something about this on linkedin, but here it goes just to make sure it reaches most of you: we wanted to thank you all, mentors, organizers and fellow chipathletes, for the great learning experience, for the support and the generous investment of time. Personally, I really enjoyed it and I'm quite sure my team did too. Even if the tapeout phase was a pain, I'm already missing the mentoring sessions and the insightful discussions, and I hope there will be a 2023 version so we can (hopefully) meet again. Best wishes to you all on behalf of team Chile/Uruguay/Argentina!

Hi, I want to edit a cell in Magic, but I face an error ( error: it is not writable). Its picture has been attached. Do you know how I can resolve it? Thanks.

I was wondering, when can we expect delivery of our manufactured chips? Just a rough estimate would already be enough

@Boris Murmann @Tim Edwards Hi, im working on the testing setup for the Chile/Argentina/Uruguay Team, I was wondering which are the specs of the evaluation boards we are going to receive with the chips. We found this https://github.com/efabless/caravel_board (Evaluation and breakout boards) and we wonder if it matches any of those.

Hi Yueting, can we talk one more time on Zoom?

@Dinesh A has left the channel

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Hello all, I just read this message, does anyone here have more info about the tapeout delays? https://open-source-silicon.slack.com/archives/C032VUYLL64/p1677180040741779?thread_ts=1677180040.741779&cid=C032VUYLL64

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The recording from the PICO Chipathon 2023 Information Session can be found here: https://ieee.webex.com/ieee/ldr.php?RCID=a876e45140900990e71f6a8da49c67f0

I'm proud to share with you our first paper from the microelectronics group at Advanced Center for Electrical and Electronic Engineering / Universidad Tecnica Federico Santa Maria in Valparaiso, Chile, in collaboration with Joel Gak's group at Universidad Católica del Uruguay and Alejandro Oliva's group at Universidad Nacional del Sur. It focuses on the implementation and implementation of a 3-level flying capacitor DCDC converter for space applications designed using opensource tools and the Skywater 130nm opensource PDK. You can find our paper in the following link: https://ieeexplore.ieee.org/abstract/document/10087013