I was wondering, when can we expect delivery of our manufactured chips? Just a rough estimate would already be enough

@Boris Murmann @Tim Edwards Hi, im working on the testing setup for the Chile/Argentina/Uruguay Team, I was wondering which are the specs of the evaluation boards we are going to receive with the chips. We found this https://github.com/efabless/caravel_board (Evaluation and breakout boards) and we wonder if it matches any of those.

Hi Yueting, can we talk one more time on Zoom?

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Hello all, I just read this message, does anyone here have more info about the tapeout delays? https://open-source-silicon.slack.com/archives/C032VUYLL64/p1677180040741779?thread_ts=1677180040.741779&cid=C032VUYLL64

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The recording from the PICO Chipathon 2023 Information Session can be found here: https://ieee.webex.com/ieee/ldr.php?RCID=a876e45140900990e71f6a8da49c67f0

I'm proud to share with you our first paper from the microelectronics group at Advanced Center for Electrical and Electronic Engineering / Universidad Tecnica Federico Santa Maria in Valparaiso, Chile, in collaboration with Joel Gak's group at Universidad Católica del Uruguay and Alejandro Oliva's group at Universidad Nacional del Sur. It focuses on the implementation and implementation of a 3-level flying capacitor DCDC converter for space applications designed using opensource tools and the Skywater 130nm opensource PDK. You can find our paper in the following link: https://ieeexplore.ieee.org/abstract/document/10087013

# ChatGPT prompt: Write a pyspice AC tank ladder oscillator # for adiabatic computational circuitry that will run in google colab # and produce a plot of the oscillator output !apt-get install -y libngspice0-dev !pip install PySpice import matplotlib.pyplot as plt import numpy as np from PySpice.Spice.Netlist import Circuit from PySpice.Unit import * # Create a new circuit circuit = Circuit('LC Oscillator') # Define the ladder network parameters n = 5 # number of stages L_value = 1@u_mH C_value = 1@u_uF # Add the ladder network to the circuit for i in range(n): circuit.L(i+1, 'n{}'.format(i), 'n{}'.format(i+1), L_value) circuit.C(i+1, 'n{}'.format(i+1), circuit.gnd, C_value) # Add a sinusoidal voltage source as input circuit.SinusoidalVoltageSource(0, 'n0', circuit.gnd, amplitude=1@u_V) # Perform an AC analysis simulator = circuit.simulator(temperature=25, nominal_temperature=25) analysis = simulator.ac(start_frequency=1@u_Hz, stop_frequency=1@u_GHz, number_of_points=500, variation='dec') # Plot the output plt.figure(figsize=(10, 6)) plt.title("LC Oscillator Output") plt.plot(np.log10(analysis.frequency), np.abs(analysis['n5'])) plt.xlabel('Log Frequency [Hz]') plt.ylabel('Voltage [V]') plt.grid() plt.show()

Hi all, I am trying to install NVSim (non volatile simulator) on CENTOS 7, but I am facing some problems. Is there anyone who can help me out

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Hi! How can I get more detailed information about the shipping of the chips? And we have an estimated date for it?

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https://www.cda.cit.tum.de/files/eda/2023_aspdac_reversible_computing_for_verification.pdf Slack Conversation

Dear @Boris Murmann, @mehdi, @jeffdi and @Tim Edwards, we just saw that the fabrication of the 2211Q run was finished 🎉 --> https://efabless.com/shuttle-status we are kind of anxious here to do some testing! we just wanted to remind you that we would like some bare die saples, how can we make sure that we will actually get some? is there anything we need to do to arrange the shipping details? thanks for your help, maybe other chipathon colleagues have similar concerns

@jeffdi is the best person to answer this.

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Is there someone I could speak to about the packaging of our chips? I have a concern about the custom pads (and the needed nitride opening) we put inside the caravel

Hello @jeffdi @Nathan Pier @Sara N, I hope you are doing fine. Talking to @Leonardo Gomes, he mentioned he managed to get some reply regarding bare die samples and packaged samples for the Chipathon 2022 chips on the 2211Q chipignite shuttle whichis in "Packaging in progress" from the last shuttle status report posted yesterday. Could you please confirm that we will get 50 bare dies and 50 packaged samples for each project? Sorry for being insistent, but it's just to make sure we know what we will get. I'm tagging @Boris Murmann and @mehdi in case they have any comments. Regards!

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Hello, could you kindly tell us when we can expect to receive the packaged ICs and when we will be notified about the delivery of the chips?

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Hello everyone, we were also hoping to get some bare dies for our project but have not heard anything since the "Packaging in progress" status tag. Has anyone had any communication with Efabless about requesting bare dies?

Hi @jeffdi, @Micah Tseng all: Does someone know when we will receive the chips of the team Chip 3 - Austria, Brazil and USA1? (cc @Christof Gindu @Rohish Kumar Reddy mitta)

Is there anyone from efabless that we can speak to in order to know what is going on regarding the lack of bare die situation? I have tried to reach all the people I could remember, but no response so far.

************ <!channel> For those concerned about receiving bare die for the SSCS 22 projects, we do have an additional wafer and will process it to get bare die for each of the projects. I’ll post a further update when those ship. Efabless had agreed to provide these after the shuttle went to fabrication, but we lost track of the request for the post processing job submission. I’ll send an update when they are going to ship. ************

Hello dear Chipathon colleagues, We received our chip and started our testing process. Exciting! Together with @italo and @Alfonso Cortés we have managed to get some first general measurements from the evaluation board while we adapt our setup to the M2 breakout board format (in the first plan, when the chips would arrive in march, the breakout board was different). And the chip seems to work! Two states of the DCDC seem fine when tested statically. We are trying to get some dynamic operation now. Unfortunately, we confused some power domains and the evaluation board doesn't work as expected anymore (specifically for the 3.3V LDO). We also have some strange behavior when we try to overwrite that voltage externally. Is there a Slack channel where we can ask about testing issues? or is there someone from Efabless or with enough experience with the latest testboards to whom we can direct the questions? @Boris Murmann @mehdi @Tim Edwards @Harald Pretl @Mitch Bailey @jeffdi

Hello All, I am working on testing my chip and I think I am missing something. I have a mixed-signal design that does not utilize the soc in the caravel. I configured the default power-up state of the gpio’s with the

user_defines.v

file to be the state that I want the gpio in. Powering up the board, there seems to be a test program already booted onto the soc that sets all the gpio to outputs and flashes them on and off (I think it might be this one: https://github.com/efabless/caravel_board/blob/main/firmware/chipignite/gpio_test/gpio_test.c). This is my surmise of what is happening because all of the digital pins are blinking and I know my ADC can’t do that ;) Does this seem reasonable? Assuming this is what is happening: is there a way to reset the gpio to their default power up states without having to boot firmware onto the soc? I’ve tried using the reset button in a variety of press/power up/power down configurations to no avail. Thanks a lot!