Hello @Tim Edwards, Regarding the high voltage devices, 5V seems to be the maximum allowed at the gate . Is this the absolute value? Or is there any way of going a bit higher? We are having some difficulties in the gate driver design for power switches and it would be of great help to have higher voltages in the gate.

Usually, the device accepts a bit (10%) more than rated. So if rated for 5V, then 5.5V as an absolute maximum is possible, but beyond that, expect sudden death of the device. Consider that the gate oxide is a few nm thick (I think 12nm for the 5V device in SKY130), which means there are gigantic field strengths. Even given that SiO2 is glass, you will blow it through.

Thanks a lot for your feedback, Harald

@Harald Pretl Do you know how it's possible to have only a max Vgs of 5V with a max Vds of 12V?

@Mitch Bailey: The breakdown across the gate is due to punch-through of the thin oxide. The breakdown of the drain is the breakdown of the P-N diode from the drain diffusion to well or substrate, and is a completely different phenomenon.

@Tim Edwards Is it possible to have Vds of 12V with Vgs under 5V? It seems to me that in this case, the Vgs is the limiting factor in determining the voltages across the device. For example, the max Vds that you could have would be 10V where Vd = 0V, Vs = 10V, Vg = 5V.

@Mitch Bailey: You can with extended-drain devices because of the resistance between the gate and the source. That's what allows the 12V, 16V, and 20V devices in this process, all of which have some kind of high resistance (usually unsalicided diffusion, but can also be a well) between gate and source.

@Mitch Bailey the explanation is what @Tim Edwards wrote: in an extended-drain MOSFET there is some electric field tweaking done using implant engineering to allow more voltage on the drain terminal (which is physically moved away from the gate in this case).

Hmmm. Thanks for the information. Now I have to figure out how to incorporate that into CVC...