I'm going through the precheck thing, and I passed all the DRC stuff, but now I'm failing this check.

LAYOUT CHECK FAILED: The GDS layout for user_analog_project_wrapper doesn't match the provided structural netlist. Mismatching modules are: ['<defunct>contact' 'TOP' 'contact$1' 'gr1' 'subcon$1']
{{NETLIST CONSISTENCY CHECK FAILED}} user_analog_project_wrapper netlist failed 1 consistency check(s): ['LAYOUT'].

I'm not really sure how to go about this one. In particular because my design apparently has some (defunct) contact cells and guard rings that aren't really some I want to describe. And also I'm not 100% sure where I am supposed to describe my TOP module.

I believe what the prechecker is comparing is the blocks in the top level of the layout to the blocks in the top verilog/spice. Does your

user_analog_project_wrapper

have a

user_analog_proj_example

? If it does, you can move your

contact

TOP

gr1

subcon

etc down one level of the hierarchy.

uh verilog or spice?

Do you have both? Did you use openlane to route the top level or is it all hand drawn?

all hand drawn

Do you have top level spice?

I see a few spice files in the netgen folder, which seem to be the generated ones

Do you have a top level spice generated from xschem?

No I'm using my own schematic editor

Is there a

verilog/gl/user_analog_project_wrapper

? Does your schematic editor produce a top level spice netlist?

this is what I have https://github.com/pepijndevos/caravel_lvds/

I don't think precheck uses the rtl verilog.

evidently not, so what is it checking?

I'd have to look at the code, but it might be using

xschem/user_analog_project_wrapper.spice

Doesn't seem like it... Adding

.subckt TOP GND VDD VDD_IO V+ V-
.ends

Xmy TOP a b c e f

to that file still results in the test complaining that there is not TOP module

What does

netgen/user_analog_project_wrapper.spice

look like?

that one says * NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A

I realize that but what subckts are defined?

well https://github.com/pepijndevos/caravel_lvds/blob/main/netgen/user_analog_project_wrapper.spice

The precheck has

if analog_gds_path.exists() and not digital_gds_path.exists():
        project_config['type'] = 'analog'
        project_config['netlist_type'] = 'spice'
        project_config['top_module'] = 'caravan'
        project_config['user_module'] = 'user_analog_project_wrapper'
        project_config['golden_wrapper'] = 'user_analog_project_wrapper_empty'
        project_config['top_netlist'] = caravel_root / "spi/lvs/caravan.spice"
        project_config['user_netlist'] = project_path / "netgen/user_analog_project_wrapper.spice"
    elif digital_gds_path.exists() and not analog_gds_path.exists():
        project_config['type'] = 'digital'
        project_config['netlist_type'] = 'verilog'
        project_config['top_module'] = 'caravel'
        project_config['user_module'] = 'user_project_wrapper'
        project_config['golden_wrapper'] = 'user_project_wrapper_empty'
        project_config['top_netlist'] = caravel_root / "verilog/gl/caravel.v"
        project_config['user_netlist'] = project_path / "verilog/gl/user_project_wrapper.v"

so for analog designs, it appears to be using

netgen/user_analog_project_wrapper.spice

. I agree with you in that it probably shouldn't be the one being used.

but... it must be comparing two things against each other right?

Or you could modify your layout so that it has one cell called

user_analog_proj_example

.

heheh

Right, it's comparing the cells in your top layout to the subckts/modules in your top netlist (ignoring some default values).

i see...

turn off all layer visibility set view depth to 1 select all instances Edit -> Selection -> Make cell

That would move the current toplevel into another cell as well right? Well what do i care....

Correct, that would take all the cells in the current top level and create a new cell named

user_analog_proj_example

.

genius! it passed the checks

Of course, you could edit the

netgen/user_analog_project_wrapper.spice

to contain the current

TOP

and

gr1

cells and maybe flatten the contact cells in the layout.

yeah 😕

The intention of the check was to put the schematic netlist in the netgen directory and then verify that with LVS. The precheck would then just check to make sure that the instances were the same. What we have done is to essentially bypass the check by creating a netlist that may not match the extracted layout, but contains the same cells.

Bear in mind that I'm the only one at efabless who knows how to do analog design, and nobody ever consults me on the contents of the precheck. I have already complained that the analog precheck is doing ridiculously stupid things.

As a result, I think there were some analog designs submitted for mpw-6 that were completely flattened, thereby avoiding the hierarchy subcircuit check.