Tried Bard ... Sure, here is an example of an LC tank circuit simulated in ngspice: Code snippet

* This is a simple LC tank circuit
* The inductor is L=1H and the capacitor is C=1uF
* The circuit is excited by a DC voltage source of V=1V

* Define the circuit elements
.define L 1H
.define C 1uF

* Define the voltage source
V1 1 0 DC 1V

* Create the circuit
L1 1 2 1H
C1 2 0 1uF

* Run the simulation
.tran 1ms 100ms

* Plot the results
.plot v(1)

hello all, so i'm trying to copy this NMOS with the connections i made in MAGIC but it only copies the NMOS cell i got from the standard cells and does not copy the connections i made, can anyone help me with this issue?

@Tim Edwards is there a way to hook up multiple VSSA pads to the same ground (same PSUB on chip) without LVS throwing a fit?

Hello everyone, I am trying to simulate current starved oscillator which gets its supply voltage from charge pump that get its clock signals from ring oscillator. ring oscillator & charge pump together only are working very well. The current starved oscillator works as well when i use a voltage source as supply voltage. but when i use the output voltage of charge pump as the supply voltage for current starved oscillator. it behaves like this. anyone have an idea what could be the problem ?

can someone help me identify the layers i'm seeing here when i pull the MiM cap (metal 3) device when i pull from the list of devices 2 in Magic, i think i'm supposed to see metal 3 layer and the capm layer but the layers here look different and i can't find layers that look the same from the layer palate in Magic, so if anyone could help me identify these layers and how i could use this cap and thanks.

@ArunAshok I have created a test circuit in sky130 for a 5V charge pump, that is ~3x the supply voltage (1.8V) you can view it online starting xschem from a directory containing the sky130 xschemrc: xschem https://raw.githubusercontent.com/StefanSchippers/xschem_sky130/main/sky130_tests/tb_charge_pump.sch

hello all, so i made this layout of the pmos lvt device with W=1um L=0.35um NF=16 M=6 , and i'm trying to do LVS but i get this result when i try to run it, can anyone help me? Note: for the layout of the PMOS, i pulled the device from the devices1 menu and just connected all the drains with all the gates making it diode connected through metal1 and all the sources together through metal2.

Hi, i saw some post on gm/Id method, an IEEE paper for the same https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=535416&tag=1 However, to plot graphs, 1. gm/Id Vs Vgs --> for gate Voltage 2. gm/Id Vs Vdsat --> i.e. VDD (also called as gate overdrive voltage) 3. gm/Id Vs gm/gds --> intresic gain 4. gm/Id Vs Vth ---> threshold voltage 5. gm/Id Vs Id/W ---> Current Density i'm searching for ngspice commands to be used with sky130, from some time. But, with few forms not able to find help. So, can anyone having example for such. It would be great help.

@Harald Pretl did a great submission for TT03 - a synthesisable analog temperature sensor. In this interview he explains how he abused the digital standard cells to get it to work:

@Tim Edwards I used metal resistors in Magic and when I went to simulate the extracted netlist in xschem I get singular matrix warnings at where the metal resistor layer touches the normal metal. The overall circuit LVSs through netgen, but I can't get the extraction to simulate, is there anything I'm doing wrong with the metal/rmetal?

People might find this talk from Tim Edwards to the CHIPS Alliance Analog Working Group about parasitics extraction in Magic interesting -

Hello all, I wonder if there is a way to reduce supply sensitivity in an inverter based Ring oscillator ? Unfortunately I can't use a differential ring oscillator due to specs on power consumption.

Hi, I was wondering if anyone with prior use of the ALIGN automated analog layout tool has been able to use the tool with some proprietary PDKs and not just SKY130. Would be a lot of help if anyone can guide us on the PDK abstraction. Thanks.

Does anyone here know, if someone has already built a negative rail supply in sky130? (prefferably -1.8V )

Hi, I'm trying to design step up switch capacitor converter. Which takes 1.5V as input and gives 4.5V as output. Operating frequency is 1kHz with 50% duty cycle. I have attached pics for the design. the input frequency is fed to the non-overlapping clock generator and then used to switch mosfets. can someone help me with my master's project, please. I have tried to change capacitor values, adding some load but didn't got as expected.

Hello, is there anyway to view the region as an operating point on schematic?

Ngspice raw file output question: Hi all, I'm trying to use the -r flag in ngspice batch mode to specify a raw file to output the simulation results to. The thing is that although ngspice clearly acknowledges the path and file name I specify on the command line because it prints a message to the console detailing it as the binary raw file to output to it doesn't ever actually write a file. Can anyone help? Thanks

Hello everyone, I am trying to find a proper sizing methodology (instead of just sweeping and observing results as transient takes a long time) for a 5 stages cross coupled charge pump operating with ultra low power (0.2V) to get good efficiency and output power of 1nW. Is there a method to get the proper sizes? I tried this method in "Eid, Majd & Rodriguez-Villegas, Esther. (2017). Analysis and design of cross-coupled charge pump for low power on chip applications. Microelectronics Journal" and sizing results didn't make any sense. in this publication it was one stage of Charge pump and in its case the input voltage was higher than Vth which is not the same as my case. Is there a way to make these relations work with such number of stages and low voltage ? Thanks

Hello @Tim Edwards, I have trouble doing lvs for a simple inverter with transistor folding of the PMOS. I seems that drain|source permutation is not working. I extract the netlist from magic with

ext2spice lvs

and

ext2spice

. I run netgen with

netgen -batch lvs "inverter_schem.spice not" "inverter_layout.spice inverter" /foss/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl lvs.log

I am using the iic-osic-tools Docker.

Hello everyone, I am simulating a first order sigma delta ADC and having a problem with SNDR and ENOB. first I got fft through ngspice and transferred it to matlab and tried 10log(power main freq/summation of power) and I got nothing valid. Also I tried SINAD on the linearized & digitized output, still nothing. Is it a right way to perform moving average on the digitized output and then run SINAD? Thanks for your replies

What's the maximum nwell to pwell voltage? Could I bias a deep n-well to e.g. 10V?

Hello! I am studying Sedra and SMithțs book on microelectronics book at the moment. What book or author would you suggest as a follow up? I am interested in understanding more complex analog blocks(differentials,mirrors,references) stuff such as common mode feedback differential pairs or cross coupled differential pairs.

Hi, @Tim Edwards @Stefan Schippers, I would like to ask about I-V curves and hot carrier effects in subthreshold region. I found the I-V curve shows exponential behavior, in particular, in the case of PFETs. Is it because of the hot carriers? However, bulk currents appear to be very small. Is there any way to check with simulation to see if the circuit is protected against the effects of hot carriers?

Hey folks, does anyone knows if there's any analog block designed with ASAP7?

hello everyone, i m working on Phase frequency detector for PLL, but i dont know how i ca evalute it or calculate the power cumsumption and the phase noise, i need help please

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Looks like the sky130_fd_pr models don't have SOA parameters. Is this the case?

Hi, I was ploting the noise density for nmos and pmos devices (to determine the corner frequency), the nmos looked ok but the pmos has a rise at the end of the frequency spectrum, if someone had any ideas of what can be happening i would appreciate it. (image of the pmos plot)

@Tim Edwards When I review the .mag file generated through Openlane flow, all the Port Label has additional information like port <Number> nsew signal <Port Direction: input/output/birectional/power/ground> << labels >> flabel metal2 s 6090 109200 6146 110800 0 FreeSans 224 90 0 0 DIn0[0] port 0 nsew signal input flabel metal2 s 6458 109200 6514 110800 0 FreeSans 224 90 0 0 DIn0[1] port 1 nsew signal input flabel metal2 s 6826 109200 6882 110800 0 FreeSans 224 90 0 0 DIn0[2] port 2 nsew signal input flabel metal2 s 7194 109200 7250 110800 0 FreeSans 224 90 0 0 DIn0[3] port 3 nsew signal input flabel metal2 s 7562 109200 7618 110800 0 FreeSans 224 90 0 0 DIn0[4] port 4 nsew signal input Where as these definition are missing while manually creating cell through magic tool. How to add the port direction and number in magic tools.? Background: I see .lef writing through magic tool include all the input/output and power declaration only when these port definition are present. PIN DIn0[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; RECT 30.450 546.000 30.730 554.000 ; END END DIn0[0] PIN DIn0[1] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; RECT 32.290 546.000 32.570 554.000 ; END END DIn0[1] PIN DIn0[2] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; RECT 34.130 546.000 34.410 554.000 ; END