For all the parameters of the NMOS/PMOS ( Vth / Vds_sat / ... that kind of stuff ), is there some table somewhere with typical values ? Because sure, I can simulate using the models (and I do) but in most text book there are formulas to "estimate" the W/L or estimate some other operating values during the design stage so I don't just enter values blindly. Or do I need to extract them from the models somehow ?

The following code works for dc sweep from 0 to 5v: .dc V2 0 5V 1m But when we run .dc V2 5V 0 1m the simulator doesn't show any error, but it also does says that the variables do not exist, while they were there when run with .dc V2 0 5V 1m Also. .dc V2 5V 0 -1m does not sweep from 5 to 0v, instead sweeps from 0 to 5v. We want to dc sweep 5v to 0v using ngspice. May we please have guidance in that

the .dc V2 5 0 -1 does calculate from 5V and go down to 0. If you simulte a circuit with hysteresis you see different waveforms going from 0 to 5 or from 5 to 0. See an example below. The ZZ signal has 2 different waveforms.

Thank you sir! Did you run it as ngspice batch can you please run it as ngspice alone, in the ngspice alone using command line. This is what I did and got two identical graphs

Why would the graph be different ? The circuit you show has no feedback/hysteresis.

Exactly this circuit has no positive feedback so no difference is seen. Another stupid circuit with hysteresis.

Please pay attention. When saving the FET drain currents these are saved with names like

i(@m.xm1.msky130_fd_pr__nfet_g5v0d10v5[id])

in the raw file. However these currents shoud more appropriately be defined as the source current. At high voltage operating conditions, where injection of carriers into the substrate occurs the drain current should be the sum of Ids + Idb , however as you can see this is not the case. I usually place ammeters in series to the device branches I want to monitor, and seems this is a good choice, otherwise if you look at the

i(@m...[id])

current you may not notice you are destroying a device due to substrate injection.

1.png

In ngspice-41 the command

.probe alli

will place ammeters into all device branches.

[newb] Any good intro links for analog + reram on skywater? All I've got is https://sky130-fd-pr-reram.readthedocs.io/en/latest/user_guide.html . And possibly .

Is GF180MCU pdf and it's mpw support analog design or digital only ?

Anybody have an analog or mixed-signal repo with a functioning build and test scripts? Can't get @Soumil Jain’s crossbar project to work.

Does anyone have use cppsim to do system level simulation? I have an issue running sue2 gui in fedora 38/Rocky linux 8, but in Windows it is running well. When I click the library at listbox, it cannot open the library and when I double click I got the error message. Does anyone know how to fix this issue?

Hello All, I hope ya’ll are having a nice day. I am working on a simple miss match Monte Carlo simulation on an inverter, but it isn’t working correctly; all of the runs are identical. I’ve read a bunch of previous posts (including one from @Stefan Schippers that mentions it might be broken) and I am not sure what I’m doing wrong. Does anyone have any ideas? I would appreciate any help or thoughts. Thanks a lot!

hello @Stefan Schippers and any other knwoledgeable colleagues here, do you know how to filter stuff in the ngspice terminal, e.g. for example to use the display command and just get the signals in one module? I'm thinking about wildcards or grep, but they didn't work when I tried to use them.

For GFMPW-1, would a mixed-signal project like a PLL be possible to implement within the digital i/o constraint? My thought would be that all of the analog logic would be internal, but the output clock could still conform to digital i/o levels?

Hello everyone. Please I need recommendations and insights from you on a project I'm currently working on. The project is a programmable gain amplifier for signal conditioning circuitry.

Previously precheck- and tapeout-clean design (October 26th) now (November 10th) throwing errors in the efabless platform

Does anybody here happen to have a design (preferably one that has been taped out) with an LVDS receiver capable of 900Mbps?

Dear all, we have been designing a bootstrap switch module on GF180, but we have encountered some issues along the way. I hope to find an answer here, we would really appreciate it. The switch is indeed working, but not as good as it should. It is worth noting that the signal is not being followed, having a voltage difference of nearly 8mV. Is this something I should expect? Or is it something that shouldn't be happening? One of the biggest problems is the charge profile given by the RC circuit formed by the output stage, and the compensation capacitor C1. This simulation has an input signal with a frequency of 1MHz, but it should be working well at 2MHz. I have seen various designs that use a charge pump to make this design faster, so I was thinking that the lack of it in the design may explain the slow RC profile. I really don't know how should I dimension the capacitor C1, or the output transistor M1, as it doesn't make any evident changes. You may find attached the simulation files on the message, as well as some pictures that illustrate the problem.

Hi channel. Is my understanding correct that skywater doesn't support CMOS image sensors fabrication? In case I'm wrong, could it produce back-illuminated CIS as well?

Dear all, From my bottomless ignorance about standard cells: would a cell as described in the link below be a safe bet for implemeting a short pulse generator? https://skywater-pdk.readthedocs.io/en/main/contents/libraries/sky130_fd_sc_hd/cells/clkdlybuf4s15/README.html I simulated it in ngspice and works fine, but I couldn't find info about the internal implementation, I'm just assuming it's a delay element from the name, and it generated longer delay than e.g. a nand4 with shorted inputs any ideas on this are appreciated!

@Tim Edwards since you are online, I take the opportunity to ask you about diodes: we need a diode for a floating gate power level shifter, I'm using a single element of diode_pw2nd_05v5 with default area 1e-12, but I'm wondering about the current allowed, is it simply defined by the metallization? or should I better put several of these in parallel for mA-level currents and current peaks?

Hello all, I'm trying to achieve LVS match of the two netlists attached using netgen, without success... my first time doing manual layout with standard cells, so no idea if anythign special should be done - for example it mentions black boxes, no idea if this is as it should be:

Circuit 1 cell sky130_fd_sc_hd__clkdlybuf4s50_2 is a black box; will not flatten Circuit 2

Warning: Equate pins:  cell sky130_fd_sc_hd__clkdlybuf4s50_2 is a placeholder, treated as a black box.

I'm working on the IIC-OSIC tools docker, with the following command: "netgen -batch lvs "/foss/designs/Open3LFCC_V2_GD12V/LS_boot_20230921/sch/sp_delay_sch.spice sp_delay" "/foss/designs/Open3LFCC_V2_GD12V/magic/tcl/sp_delay_lyt.spice sp_delay" /foss/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl lvs_delay.log" I'm attaching below the .log file in case anyone can take a look, any help would be greatly appreciated!

lvs_delay.log

@Mitch Bailey @Tim Edwards maybe you have ideas on how to debug this

colleagues, is ubuntu 22 lts ok to go with openlane, sky130 pdk and all tools for analog? I'm on mac m1 and it is giving me hard times, so thinking of vmware ubuntu 22. but having experience with ROS1 which is good on ubuntu 20 and not ok with 22, I just want to make sure that 22LTS is not 'too recent' to run all toolchain and editor tools for schematics

Has anyone ever attempted to make transient spice simulations including noise? If so, I would be very grateful for some exchange!