I'm having a

P-diff distance to N-tap must be < 15.0um (LU.3)
All nwells must contain metal-connected N+ taps (nwell.4)

but any via type thing I try to make only makes matters worse. In magic I see a substrate contact, a deep n-well region, and mcon. From the layer diagram floating around it looks like you just plonk down some licon but... everything I try just makes it worse.

tap layer. If you're using standard cells, sky130_fd_sc_hd__tapvpwrvgnd_1 You'll need the right implant.

When I look at the guard ring that magic generates, it has a nwell, then

tap

as you say, and then

nsdm

which is N+ diffusion right? And then it has

licon1

and

li1

on top.

@Pepijn de Vos: In magic,

nsd

(n-substrate-diffusion) with an

nsc

(n-substrate contact) connects an n-well to local interconnect. (

psd

with a

psc

contact connects substrate or p-well to local interconnect). I have a selection for "substrate contact" in the device generation menu. I suppose I should add another entry for "well contact". It's basically just the "Deep nwell region" selection without the deep nwell (so you could use "Deep nwell region" to create the guard ring and then erase the deep nwell). There's a lot more that could be done with the device generator scripts in magic for sky130. I had a proposal for Google Summer of Code to do device generator development, but it got rejected.

Well here you go, n-well generator https://github.com/RTimothyEdwards/open_pdks/pull/259

They actually do stuff. In some processes the

hvi

layer (or equivalent) is just used under a transistor gate to isolate the gate region for growing thick oxide. But SkyWater also changes the diffusion implants on high voltage areas so that the P-N junctions can withstand higher voltages, so there is really a high-voltage type diffusion and high-voltage type well.

So if my guard ring is covered in

hvi

why does it complain that my diffusions are not HV?

Is the entire nwell covered in

hvi

, including all devices inside the guard ring?

yea I just drew a box of the same size as the nwell

There could be an issue if your devices inside the nwell are in separate subcells; you would need to have the

hvi

layer inside the subcell so that magic knows that it is a high-voltage device when it reads the subcell.

ah maybe my hvi layer is in the wrong cell lemme see

Just be aware that magic likes to consolidate layers in the same cell to figure out what kind of device exists; most devices then have one drawn type per extracted device. So "nfet" and "mvnfet" are different drawn devices in magic. But to get those derived types from an input GDS that was not drawn in magic, it is necessary to have all GDS layers that uniquely define the device type in the same cell. There are ways to get around that but it requires somewhat complicated coding of the GDS input rules in the magic tech file, and I don't think I have those rules for distinguishing low- and high-voltage FETs. So the gate poly, diffusion, N- or P-implant, and HVI implant all need to be in the same subcell.

yea if I put hvi inside the guardring subcell it... proceeds to a new error

N-well overlap of MV N-tap < 0.33um (diff/tap.19)

Yes. There are a different set of DRC rules for high voltage diffusion and wells.