Mitch Bailey
07/01/2022, 4:20 PMnetgen/user_analog_project_wrapper.spice
to check the structure of the layout. They should have the same Tim Edwards
07/02/2022, 2:22 AMTim Edwards
07/02/2022, 2:25 AMuser_analog_project_wrapper.spice
is the layout-extracted netlist? That would guarantee the hierarchy but it would also be a pretty useless precheck.Mitch Bailey
07/02/2022, 2:38 AMMitch Bailey
07/02/2022, 2:58 AMcaravel_analog_user_project
repo comes with an netgen
directory that contains user_analog_project_wrapper.spice
. This file contains one subcircuit user_analog_proj_example
. If the user does not change this file and submits a design that also has one subcell, user_analog_proj_example
, the check will pass. If the user has a different hierarchy, they can either create a new layout user_analog_proj_example
and put everything in there or (preferably) replace netgen/user_analog_project_wrapper.spice
with a netlist that matches their design (hopefully from a schematic editor and not a copy of the extracted netlist).
The real problem, IMHO, is that device level LVS is not part of the precheck. I don't think most foundries require LVS clean designs because of all the issues involved, but it may be something we can implement for mpw.Tim Edwards
07/02/2022, 2:47 PMMitch Bailey
07/02/2022, 3:45 PMPart of this problem is that the openlane digital flow forces the example design to be replaced with the new user design,There are several digital designs on mpw6 that contain the default named
user_proj_example
cell. Are you saying that the precheck checks the contents of this cell in addition to the contents of user_project_wrapper
?Tim Edwards
07/02/2022, 4:54 PM