When submitting analog designs for the mpw shuttle...
# analog-design
m
When submitting analog designs for the mpw shuttles, the precheck uses
netgen/user_analog_project_wrapper.spice
to check the structure of the layout. They should have the same hierarchy subcells at the top level. (Ideally they should also be an LVS match.)
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t
Is it assuming the same hierarchy for all cells all the way down to the bottom? Because I have never seen nor created any chip-level design for which that was true.
Or is it expecting that
user_analog_project_wrapper.spice
is the layout-extracted netlist? That would guarantee the hierarchy but it would also be a pretty useless precheck.
m
Sorry for the misunderstanding. I've corrected it.
The
caravel_analog_user_project
repo comes with an
netgen
directory that contains
user_analog_project_wrapper.spice
. This file contains one subcircuit
user_analog_proj_example
. If the user does not change this file and submits a design that also has one subcell,
user_analog_proj_example
, the check will pass. If the user has a different hierarchy, they can either create a new layout
user_analog_proj_example
and put everything in there or (preferably) replace
netgen/user_analog_project_wrapper.spice
with a netlist that matches their design (hopefully from a schematic editor and not a copy of the extracted netlist). The real problem, IMHO, is that device level LVS is not part of the precheck. I don't think most foundries require LVS clean designs because of all the issues involved, but it may be something we can implement for mpw.
t
The complexity of dealing with unknown analog design flows is why we don't do an LVS check. It is all too easy to make a layout in an arbitrary layout tool that cannot be correctly extracted by magic, as you well know, which makes it nearly impossible to enforce that LVS can be run on the precheck side. Although maybe it should be a default condition that can be forced to be overridden if needed. Although as it currently stands, magic and klayout are the only open source tools that can generate an extracted netlist, so there is a point to be made that if a design cannot be correctly extracted by either of those tools and run through LVS (either in netgen or klayout) and pass, then the design does not belong in an open MPW. I think the intent of the current netlist check for analog designs is to make sure that the designer has removed the example netlist and replaced it with something that is actually related to the user project. In the past we have seen too many projects that still had the example files in them. Part of this problem is that the openlane digital flow forces the example design to be replaced with the new user design, but there is no such analog flow, so no requirement that the original example files should be removed.
๐Ÿ‘ 1
m
Part of this problem is that the openlane digital flow forces the example design to be replaced with the new user design,
There are several digital designs on mpw6 that contain the default named
user_proj_example
cell. Are you saying that the precheck checks the contents of this cell in addition to the contents of
user_project_wrapper
?
t
I was speaking of the project wrapper, not the project example. There is some sort of check for digital projects that the wrapper is not the one with the user project example in it.
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