Happy thanksgiving every one! Hi @Tim Edwards, I’m inputting the full RC extraction codes you shared (as below) line by line in magic 8.3.315 for extracting my flat design

bgr_top_flat.mag

. When I’m inputting line

extresist

, the error messaged popped up (see attached figure). This

bgr_top_flat.mag

file passed lvs check already, so I don’t know why it suggests “missing terminal connection” still and error in extracting some nodes. Looking forward to your suggestions.

load bgr_top_flat.mag
select top cell
extract all
ext2sim labels on
ext2sim
extresist tolerance 10
extresist
ext2spice lvs
ext2spice cthresh 0
ext2spice extresist on
ext2spice

The only thing I see in the netlist related to specific error messages is that a lot of ground connections are labeled simply

VSS

instead of one of the ground network terminals (e.g.,

VSS.t104

). I expect it doesn't really understand how to extract the substrate as a network. This seems to be true for every device that has a substrate connection, including nFETs, PNP bipolars, and resistors (which are modeled as 3-terminal devices). The pFETs have proper connections to terminals of the

VDD

network, so in theory it ought to be able to do the same thing with the substrate, but I'm not sure why. The bipolar collector connection is probably the worst case here for inaccuracy; everywhere else using the generic name

VSS

(which would equate to the ground net close to the pin name) for a substrate node won't introduce much inaccuracy into the simulation.

Thanks @Tim Edwards , can I ignore this error message and generate the RC extracted netlist? Or maybe I can extract C only instead if that would be helpful.

You can (sort of) ignore the error. Extracting only C would be a step backwards---you have a lot of resistive wiring in your design and you need to be able to see what those resistances do to the bandgap simulation. But with the issue above, you won't see any resistance from the bipolar collector to ground. I don't expect that will have much impact on the bandgap behavior, though.

Hi @Tim Edwards , I ignored the error message for pex and ran monte carlo post-layout simulation, while the mean value of output voltage “v(bgr)” for the bandgap reference circuit I got is 1.21V, which is far away from my specification 1V. If I only do C extraction and ran mc simulation, the mean value is 0.96V, which is good. The steps I did post layout simulation is as below: 1. Use extract full RC in magic from “bgr_top_flat.mag” to generate pex file “bgr_top_flat.spice” 2. run

ngspice tran.sp

to generate v(bgr) raw file. 3. run

python2 raw-txt.py

to check mean value of v(bgr). I attached all files I used in the zip for your reference. If above steps are valid, for a closer look check why the “v(bgr)” from the post-layout differs a lot from its pre-layout simulation, where would you recommend me to check first? Appreciate your advice!

Yueting, there is no need to run Monte Carlo to debug your problem, just op. If there is an R only extraction I would try that as well. C is meaningless for the problem you are having. What are the input voltages of the bandgap's diff pair with and without parasitic R?

@Yueting Li: I gather from looking at the layout that this has been done like a standard cell place & route. Be aware that place & route tools are designed for digital circuits; they assume that wires carry no (appreciable) DC current, because all wires terminate on digital gates. So the goal of the place & route tool is to minimize capacitance. Your bandgap produces a steady-state value; you don't need high speed and you don't need low capacitance. The highest capacitance you can get on your power supplies and your bandgap output are both to your advantage. But you do need to keep resistances low, because the bandgap depends on resistor ratios, and every bit of stray parasitic resistance works against having that proper ratio of resistors. For example, your power and ground straps are run in metal1 only (sometimes strapped to local interconnect, which doesn't help much), and only in the horizontal direction. The metal1 width is 0.6um and the width of the circuit is roughly 215um, so from the power ring to the center is 180 squares at 0.125 ohms/square, or 22 ohms. Which is not huge, but for a precision circuit like a bandgap, you want that value to be as close to zero ohms as you can reasonably make it, and simply strapping your power supply lines to wide lines of thick top metal all over the circuit is easy to do and will reduce the power supply resistance to a fraction of an ohm. Your resistors are 7.9 x 2.9 um, or less than three squares. For best matching, ideally you should have at least 5 squares, preferably 10, for the resistor length; all resistors should be in an array with exactly the same spacing, and the array should have a row or column of dummy resistors on every side. Routing over resistors should be avoided unless you can do so in a regular pattern, or with a metal shield layer between the routing and the resistor. All contacts should have multiple cuts. I realize that if OpenROAD did the routing, then this is a missing function in the router. If you can get the router to use wide track spacing and wide wires, then it will make a better layout. Just taking a random route between resistors as an example, I see a route with a resistance that I can hand-calculate to about 120microns m1 and m2 at a wire width of 0.14um, which is around 850 squares. That means the wire is 100 ohms. The resistors are only 10kohm each, so that's only a 1% error, but it's 1% error on what is supposed to be a precision resistor ratio. I think the worst case is where you have long arrays of transistors where the sources and drains are only connected through local interconnect. In one of your long transistor arrays, there is a 75um distance between the endmost FET and the wire connecting it to other circuits. The local interconnect wire is 0.3um, so that's 250 squares at 12.8 ohms/square, or 3.2kohms.

Hi @Tim Edwards, thanks for your thoughtful inputs. Yueting is using digital P&R (Innovus), but there is an algorithm wrapped around this that minimizes overall netlength and forces matched mos pairs to be close to each other. The IR drop in the resistor branches may indeed be the culprit, since I think these are not looked at by the algorithm. @Yueting Li, you'll need to go in and measure the voltages and add metal straps where needed. There may also be issues with having an insufficient number of contacts.

@Tim Edwards @Boris Murmann It’s the first time I did the analog layout, and thanks so much for your feedback that I learned a lot. Those are very good suggestions that I’ll check points (metal layer, device size, and multiple contact cuts) you mentioned together with voltage probe in the circuit.

I understand the goal of getting automatic place and route tools to create analog layouts, and I'm all in favor of it! Just be sure you're aware where the tools are optimized for digital circuits and why that's often not the best for analog circuits.