Hi @Mitch Bailey /@Tim Edwards When I am extracting the layout hierarchically, how can I preserve the port names. I would like to get the same port names when I extract from the top level file as well. (This is when I extract module level magic file) .subckt VLS_16x2_1808_layout_WIRE_EXT IN1[15] IN0[15] IN0[14] IN1[14] IN1[13] + IN0[13] IN0[12] IN1[12] IN1[11] IN0[11] IN0[10] IN1[10] IN1[9] IN0[9] IN0[8] IN1[8] + IN1[7] IN0[7] IN0[6] IN1[6] IN1[5] IN0[5] IN0[4] IN1[4] IN1[3] IN0[3] IN0[2] IN1[2] + IN1[1] IN0[1] IN0[0] IN1[0] V4 V3 V2 V1 ENABLE OUT[1] OUT[0] OUT[3] OUT[2] OUT[5] + OUT[4] OUT[7] OUT[6] OUT[9] OUT[8] OUT[11] OUT[10] OUT[13] OUT[12] OUT[14] OUT[15] + VDD_LOW VSS VDD_HIGH (This is when I extract from top level magic file) .subckt VLS_16x2_1808_layout_WIRE_EXT IN0[13] IN0[12] IN0[11] IN0[10] V3 V2 OUT[1] + OUT[2] OUT[5] OUT[4] OUT[7] OUT[6] OUT[9] OUT[8] OUT[11] OUT[10] OUT[13] OUT[12] + OUT[14] OUT[15] VLS_16x2_1708_layout_1/VLS_1x2_1708_layout_0[6]/VLS_1v8to5V_D1_And_VoltSelector_1407_layout_1/VLS_g5D10_LV1v8_HV5V_1/DATA_OUT_HV_5V + VLS_16x2_1708_layout_1/VLS_1x2_1708_layout_0[2]/VLS_1v8to5V_D1_And_VoltSelector_1407_layout_1/decoder_4x1_with_pmos_switch_LV_support_11_07_layout_0/decoder_D1_g5d10_10_07_0/and_D1_W0p840_L0p5_10_7_1/a_764_n236# + VLS_16x2_1708_layout_1/VLS_1x2_1708_layout_0[6]/VLS_1v8to5V_D1_And_VoltSelector_1407_layout_1/decoder_4x1_with_pmos_switch_LV_support_11_07_layout_0/decoder_D1_g5d10_10_07_0/IN0_inv + VLS_16x2_1708_layout_1/VLS_1x2_1708_layout_0[6]/VLS_1v8to5V_D1_And_VoltSelector_1407_layout_0/VLS_g5D10_LV1v8_HV5V_0/a_522_n108# + VLS_16x2_1708_layout_1/VLS_1x2_1708_layout_0[2]/VLS_1v8to5V_D1_And_VoltSelector_1407_layout_0/decoder_4x1_with_pmos_switch_LV_support_11_07_layout_0/decoder_D1_g5d10_10_07_0/and_D1_W0p840_L0p5_10_7_0/a_764_n236# + VLS_16x2_1708_layout_1/VLS_1x2_1708_layout_0[2]/VLS_1v8to5V_D1_And_VoltSelector_1407_layout_0/decoder_4x1_with_pmos_switch_LV_support_11_07_layout_0/decoder_D1_g5d10_10_07_0/IN1_inv + VLS_16x2_1708_layout_1/VLS_1x2_1708_layout_0[2]/VLS_1v8to5V_D1_And_VoltSelector_1407_layout_1/decoder_4x1_with_pmos_switch_LV_support_11_07_layout_0/decoder_D1_g5d10_10_07_0/and_D1_W0p840_L0p5_10_7_2/a_764_n236# + VLS_16x2_1708_layout_1/VLS_1x2_1708_layout_0[6]/VLS_1v8to5V_D1_And_VoltSelector_1407_layout_0/VLS_g5D10_LV1v8_HV5V_0/inverter_D1_g5v10_1/IN + VLS_16x2_1708_layout_1/VLS_1x2_1708_layout_0[5]/VLS_1v8to5V_D1_And_VoltSelector_1407_layout_1/decoder_4x1_with_pmos_switch_LV_support_11_07_layout_0/V_SEL_g5D10_W0p840_L0p5_11_7_layout_2/inv_D1_W0p840_L0p5_10_7_0/OUT + OUT[0] VLS_16x2_1708_layout_1/VLS_1x2_1708_layout_0[2]/VLS_1v8to5V_D1_And_VoltSelector_1407_layout_1/decoder_4x1_with_pmos_switch_LV_support_11_07_layout_0/decoder_D1_g5d10_10_07_0/IN1_inv + IN1[14] IN1[0] IN1[15] IN1[1] VLS_16x2_1708_layout_1/VLS_1x2_1708_layout_0[2]/VLS_1v8to5V_D1_And_VoltSelector_1407_layout_0/decoder_4x1_with_pmos_switch_LV_support_11_07_layout_0/decoder_D1_g5d10_10_07_0/OUT2

Magic will add ports as needed depending on what connections are made from the top level. If you extract with parasitics, you can get many more ports because there are parasitic capacitances connecting down to nodes in the middle of the subcell. I expect that's what is causing the additional ports. But I can't be certain without a full reproducible example.

Thank you so much.