Hello everyone, when I run qflow on my verilog design it creates a folder named "layout" where you have .gds and .mag files which you can open in magic and view, however when I try to do this then I do not see the standard cell gates and on the console window it says that it is unable to read them, what could be the issue.

Hello, Is there anyway to resize the top cell so that it encompasses just the circuit. Some how I made it so that the top cell is much bigger than the actual area consumed by the lower cells.

Hello @Tim Edwards @Mitch Bailey Excuse me, can you please double check out the DRCs with me!. It is clean on my machine when i used the button in the shown list? is it OK?

Hello @Tim Edwards @Mitch Bailey Can you guide me to generate a .lef file from GDS, please? Is there a specific command? Thanks in advance.

I have a question about ext2spice port numbering. The documentation says subcircuit ports will be in the order of the port numbers, but I've noticed that Vdd and GND become the last two ports irrespective of their port number. My question is whether there are other special cases -- or whether I have just not found the right documentation. The problem arises in keeping layouts in synch with designs that originated with ngspice circuits. (In chasing this down, I resorted to editing the mag file to change port numbers more efficiently.)

Hi SRAM layout rules are different from digital design rules. In sky130 where can i find SRAM layout design rules??

What does this error mean? I got it when I imported a SPICE netlist to magic

@Tim Edwards I want to use magic to flatten a .mag file without access to a X-Server. At the moment I am using the commands "select top\nexpand\nflatten $flat\nload $flat\nsave\n" but I get the error "Crosshair not in a valid window for this command". Any ideas?

Hmm, it seems to work without the "select top" command at the top. I just hope that it always works and that it doesn't randomly fail someday

Hi, does anyone know how to get the name of the painted layer? It can be very difficult to find the layer name from the palette by eye.

@Tim Edwards What is the best way in

magic

to draw non-manhattan lines, like in octagonal inductors? (w.o. resorting to zigzag :-))

@Tim Edwards I'm working with isolated NMOS devices right now with GF180 PDK, and it extraction is weird. I have this self-oscillating voltage doubler here. It is made of a central ring oscillator, which powers a positive supply VHI and a negative supply VLO. If I extract only the ring oscillator, it is ok. But when I extract the whole voltage doubler, the ring oscillator gets a new port which isn't connected anywhere. Why?

Hi, does anyone know how I can independently have a multiplicity transistor to be able to apply the interdigitation technique when extracting the transistors from the spice in magic? since when extracting they all stick together and I cannot move them independently

Hi, Does anyone know how I can separate two pins that accidentally overlapped?

Yeah, load the mag file in a text editor. Search for one of the names and delete the line.

Hello, does anyone know why when I extract the spice from magic, the assigned labels do not appear, the subcircuit does not connect what is inside Ext2spice lvs Ext2spice cthresh infinite Ext2spice resistor off Ext2spice

IMG_0063.jpg

Hi @Tim Edwards I keep having frustrating issues with magic to do with paths to various sub cells in my design (see attached picture). I always open magic in the same folder to be consistent but I just don't understand what the issue is. How does magic track paths to files internally and what is the solution here? cheers!

image.png

Here is an issue related to extraction to ngspice: Extracting a "Caravan" project yields a .spice file about 1000 lines long, including the two lines below. The issue is "**FLOATING" in the first line. In the Caravan wrapper: C187 ip_bar_0[2]/ip_cgn_0[4]/Clx io_analog[10] 2.01f **FLOATING In subcircuit ip_cgn: C1 Clx GND 2.01f As humans, we see magic attempting to extract capacitance between node Clx and GND. Unfortunately, a different naming convention is used in the top-level Caravan file and the cell or subcircuit called ip_cgn. The diagram attached (mixed Magic and Powerpoint) shows the context. The dash-dot line is a boundary between the Caravan wrapper and a subcircuit. The node io_analog[10] is an input port to the wrapper that connects to the subcell in the upper-left through a port named GND. The other net is Clx, which is entirely local to the subcell and highlighted (white outline) in the diagram. The red-text "dielectric" in the diagram is the location of the capacitor between these nodes. The m2 lines extend a long way below the bottom of the image. As humans, we recognize "ip_bar_0[2]/ip_cgn_0[4]/Clx" as notation for accessing Clx two levels down the hierarchy. While ngspice netlists allow '/' in node names, they are interpreted as ASCII rather than a directive to descend the hierarchy. While the actual Clx node is not floating, as far as ngspice is concerned there is a floating node whose name might as well be 28 random characters.

Is there a way to extract parasitic well junctions (e.g. dnwell - pwell) with magic?

I'd have two questions on the usage of magic:

1. Is there a command to print a list of labels? 2. Is there a command to print the name of the edit cell (on my display there is no difference of colors between edit cell an other cells)?

I have some simple metal-only cells in an array in GDS that aren't extracted by magic, but are seen by the consistency precheck, causing a consistency failure. When I run

flatten -doinplace <name>

it simply deletes the array. How do I flatten the cells or convince magic to extract them to spice despite containing no devices?

Hi. So I'm trying to figure out an issue I have with DEF -> GDS/LEF (made by OpenLane2 using magic).

Basically for some pins the name of the pin end up ... wrong, it uses the name of an inside net inside.

@Tim Edwards Another issue that you might already be aware of, but I got LEF extraction "hanging" (seemingly never finishing, left it for hours ...) on some GDS ?

It was working fine with magic 394 (but then the resulting LEF had less "nice" shapes for the extracted pins ... somehow the whole metal area on the same layer was extracted as pin and not just the actual pin area). With magic 400 the pin area is correct but LEF generation doesn't finish.

What layer do I need to make a proper tap for pmos devices in magic? I have imported a design from Cadence Layout XL, but device taps that pass those DRCs have layers are not clean in magic checks. For example, placing pdiff to fix N-tap overlap of N-tap contact < 0.12um (licon.7) results in a "Can't overlap those layers" error. Other commenters have mentioned a "psd" layer, but for some reason I don't have that naming convention, only pdiffusion. A number of other layers have similarly strange names.

@Tim Edwards Is there a possibility in magic to mark a metal capacitor structure, so that when extracting a netlist for LVS, that this cap is written into the netlist? Something like a marker layer for metal caps.