Stephen Sigdox
10/23/2023, 4:34 AMtnt
10/25/2023, 3:43 PMHADASSA JULIANA DA COSTA GOMES
10/26/2023, 8:21 PMtnt
10/27/2023, 3:09 PMAmirhossein zanjani
10/30/2023, 9:07 AMAmirhossein zanjani
10/31/2023, 8:13 AMAmirhossein zanjani
11/03/2023, 12:12 AMEllen Wood
11/04/2023, 10:32 AMEllen Wood
11/05/2023, 1:28 PMEllen Wood
11/05/2023, 1:29 PMEllen Wood
11/05/2023, 1:31 PM_0p35
. These were generated by the device generator in Magic, and in the layout it definitely looks like the suffix is present on these cells:Ellen Wood
11/05/2023, 1:31 PMEllen Wood
11/05/2023, 1:34 PM_0p35
suffix:Ellen Wood
11/05/2023, 1:35 PMEllen Wood
11/05/2023, 6:54 PMuser_project_wrapper.gds.spice.
In both layout and schematic, the net associated with the Deep N Well is labelled (TXRX_B_POS_via_R
), but not ported out, so the .spice file from Xschem doesn't show it. Therefore we have LVS mismatches because every cell in the Layout has one extra pin in their pin list than in reality. The behavior is similar to what we've seen when the parasitic extraction is on in Magic. Is there any way to stop this happening please? 🙂Ellen Wood
11/05/2023, 6:57 PMEllen Wood
11/05/2023, 6:58 PMEllen Wood
11/05/2023, 7:08 PMTim Edwards
11/06/2023, 2:16 AMEllen Wood
11/07/2023, 6:51 AMSimon Waid
11/08/2023, 4:09 PMAmirhossein zanjani
11/09/2023, 3:19 PMÇağrı Gürleyük
11/10/2023, 9:06 AM권미정
11/11/2023, 12:45 PMMitch Bailey
11/11/2023, 2:07 PMsky130_fd_pr__nfet_01v8_YCY3T5
is not a mosfet, but a subckt containing 4 mosfets. At the parent hierarchy, these are probably connected in parallel, but at this level, there are separate ports for each source/drain.
I suspect the problem might come from a missing setup file when executing netgen. I suggest
netgen "tah.mag.spice.txt tah" "tah.sch.spice.txt tah" $PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl
If you can share your comp.out
file, I might be able to offer more suggestions.Harald Pretl
11/13/2023, 4:47 PMTom
11/15/2023, 10:18 PMTom
11/21/2023, 9:49 PM.option scale=5n
at the top of a paracitic extracted netlist for GF180mcuTom
11/23/2023, 9:03 PMdin[0].t0
in the resistor extracted netlist goes to the gate of the nFET but I can'd find an equivalent path to the pFET, which aligns with the failing simulation.
My extraction procedure is as follows:
load $MAG_CELL
flatten ${CELL_NAME}_pex
load ${CELL_NAME}_pex
box values 0 0 0 0
extract all
ext2sim labels on
ext2sim
extresist tolerance 10
extresist all
ext2spice lvs
ext2spice cthresh 0
ext2spice extresist on
ext2spice -o $OUTPUT_FILE_NAME
exit
Thanks in advance!정진형학부생
11/27/2023, 5:55 AM