Hello @Tim Edwards, I have a rather random (and probably uninformed) question. After the meeting on Friday where the via resistance was discussed and you mentioned that all vias in this PDK are squares of standard size, it occurred to me that I have been drawing vias of variable size and further the

gencell

for things like caps also draws vias of variable size. So could you tell me what is actually fabricated when vias of larger than the minimum size are submitted? For example, in this capacitor generated from

gencell

is that long via on the right replaced with a single small square via? Or multiple small square vias? Thanks a lot!

vias in magic are not true vias, but rather regions that will be filled with properly sized and spaced vias. To see the actual vias, either look at the converted gds or maybe try the magic

cif see via1

command (I haven’t tested this). See http://opencircuitdesign.com/magic/commandref/cif.html

@Mitch Bailey thank you! That is super helpful.

maybe

cif see none

?

Hmmm….that doesn’t work. It’s not a big deal. Thank you!

@Tim Edwards is there a way to turn off

cif see

?

Ah @Tim Edwards , thank you!