Hello all We are finding issues in pulling our latest repo t open-source-silicon.dev #ieee-sscs-dc-22

Hello all, We are finding issues in pulling our la...

Jorge Marin

11/07/2022, 7:44 PM

Hello all, We are finding issues in pulling our latest repo to the Efabless platform. Since out .gds.gz is a bit bigger than the github limita of 100MB, we are using git-LSF to upload big files. We manage to get the file to the github repo, but doing "Git Pull" on the Efabless platform generates a user_project_analog_wrapper.gds.gz with 134bytes size. When doing precheck, it fails. Does the Efabless platform allow files uploaded to git-LSF? if the answer is yes, what could be wrong in out uploading flow and how to debug it? @jeffdi @Tim Edwards @Mitch Bailey

Tim Edwards

11/07/2022, 10:50 PM

No, LFS caused a bunch of problems and while we tried it initially, we had to abandon it. There are ways to work around the large file problem, like writing an Oasis file, although @jeffdi will have to tell you what works with our submission system.

Jorge Marin

11/08/2022, 12:54 AM

We would really appreciate your help, can you give us more info about how to do this @Tim Edwards @jeffdi? What does the Oasis file do and where can we find a good reference about this? Our tapeout is next monday!

Mitch Bailey

11/08/2022, 1:39 AM

Try

make compress

Jorge Marin

11/08/2022, 2:22 PM

hello, I'm doing "make compress" from my project folder, but I get the following error, what am I doing wrongly?

Jorge Marin

11/08/2022, 5:33 PM

Ok, solved it after doing make install Make compress splits the .gz un two files with max 100mb size, so now i can pull and do precheck online

👍 1

Jorge Marin

11/09/2022, 11:43 AM

hello @Tim Edwards, @Mitch Bailey, @jeffdi sorry to keep asking about this, but after being able to Git Pull our 108MB gds file compressed and splitted by "make compress", the precheck takes a huge amount of time, it's actually still running since yesterday. PLEASE could you check what could be wrong? this is a potential showstopper for our chipathon design this is our project: https://platform.efabless.com/projects/1427 please see below the log of the current precheck run, it gets stuck in the Klayout BEOL check; the first time we waited 11 hours and then I stopped the check, the second time has been running the check for the whole night:

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[11/08/22 19:14:43 PST] SUBMITTED
                


        
    
        
            

            [11/08/22 19:14:55 PST] STARTED
                


        
    
        
            

            [11/08/22 19:14:58 PST] PROJECT GIT INFO
                Repository: <https://github.com/JorgeMarinN/3LFCC_AC3E_Tapeout.git> | Branch: sscspico | Commit: f88c910194aade382db0d6030ebe52e6f1b1e40b


        
    
        
            

            [11/08/22 19:14:58 PST] EXTRACTING FILES
                Extracting compressed files in: sscs_pico_chip_6


        
    
        
            

            [11/08/22 19:15:02 PST] PROJECT TYPE INFO
                analog


        
    
        
            

            [11/08/22 19:15:03 PST] PROJECT GDS INFO
                user_analog_project_wrapper: 746c89fcdc82c63ea002ee880f6e5c2529656ffe


        
    
        
            

            [11/08/22 19:15:03 PST] TOOLS INFO
                KLayout: v0.27.10 | Magic: v8.3.315


        
    
        
            

            [11/08/22 19:15:03 PST] PDKS INFO
                PDK: sky130B | Open PDKs: 05af1d05227419f0955cd98610351f4680575b95 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb


        
    
        
            

            [11/08/22 19:15:03 PST] START
                Precheck Started, the full log 'precheck.log' will be located in 'sscs_pico_chip_6/jobs/mpw_precheck/c0790e08-6460-4ac2-a71a-9dc165a8c7f0/logs'


        
    
        
            

            [11/08/22 19:15:03 PST] PRECHECK SEQUENCE
                Precheck will run the following checks: [Makefile, Consistency, GPIO-Defines, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]


        
    
        
            

            [11/08/22 19:15:03 PST] STEP UPDATE
                Executing Check 1 of 11: Makefile


        
    
        
            

            [11/08/22 19:15:03 PST] MAKEFILE CHECK PASSED
                Makefile valid.


        
    
        
            

            [11/08/22 19:15:03 PST] STEP UPDATE
                Executing Check 2 of 11: Consistency


        
    
        
            

            [11/08/22 19:15:07 PST] NETLIST CONSISTENCY CHECK PASSED
                caravan netlist passed all consistency checks.


        
    
        
            

            [11/08/22 19:15:07 PST] NETLIST CONSISTENCY CHECK PASSED
                user_analog_project_wrapper netlist passed all consistency checks.


        
    
        
            

            [11/08/22 19:15:07 PST] CONSISTENCY CHECK PASSED
                The user netlist and the top netlist are valid.


        
    
        
            

            [11/08/22 19:15:07 PST] STEP UPDATE
                Executing Check 3 of 11: GPIO-Defines


        
    
        
            

            [11/08/22 19:15:08 PST] GPIO-DEFINES CHECK PASSED
                The user verilog/rtl/user_defines.v is valid.


        
    
        
            

            [11/08/22 19:15:08 PST] STEP UPDATE
                Executing Check 4 of 11: XOR


        
    
        
            

            [11/08/22 19:17:40 PST] XOR CHECK UPDATE
                Total XOR differences: 0, for more details view sscs_pico_chip_6/jobs/mpw_precheck/c0790e08-6460-4ac2-a71a-9dc165a8c7f0/outputs/user_analog_project_wrapper.xor.gds


        
    
        
            

            [11/08/22 19:17:40 PST] XOR CHECK PASSED
                The GDS file has no XOR violations.


        
    
        
            

            [11/08/22 19:17:40 PST] STEP UPDATE
                Executing Check 5 of 11: Magic DRC


        
    
        
            

            [11/08/22 19:18:13 PST] MAGIC DRC CHECK PASSED
                The GDS file, user_analog_project_wrapper.gds, has no DRC violations.


        
    
        
            

            [11/08/22 19:18:13 PST] STEP UPDATE
                Executing Check 6 of 11: Klayout FEOL


        
    
        
            

            [11/08/22 19:19:28 PST] KLAYOUT FEOL CHECK PASSED
                The GDS file, user_analog_project_wrapper.gds, has no DRC violations.


        
    
        
            

            [11/08/22 19:19:28 PST] STEP UPDATE
                Executing Check 7 of 11: Klayout BEOL

Mitch Bailey

11/09/2022, 1:10 PM

Your design has a large flattened area which may be resulting in long run times. If there are errors, I think they should be output to a log somewhere. Have you tried the local precheck?

Jorge Marin

11/09/2022, 5:21 PM

hello @Mitch Bailey, thanks for replying I'm running the local precheck and I get the consistency fails (but these were a precheck issue, I believe) but also this error in the Klayout FEOL, please see the attached screenshot. So, in summary, we don't get to the Klayout BEOL which is the step that is taking forever in the online precheck. Do you have any ideas what this could be?

Jorge Marin

11/09/2022, 5:22 PM

fyi @Alfonso Cortés @aquiles viza

Mitch Bailey

11/09/2022, 10:13 PM

Looks like it can’t find the klayout FEOL output. Can you check

precheck_results/<timestamp>/logs/klayout_feol_check.log

to see if you can find out why?

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