Hi I’m getting this error in the openlane flow (user_porject_wrapper)

[STEP 14]
[INFO]: Writing Verilog...
[STEP 15]
[INFO]: Running Detailed Routing...
[ERROR]: during executing openroad script /openlane/scripts/openroad/droute.tcl
[ERROR]: Exit code: 1
[ERROR]: full log: ../home/mxmont/Documents/Universidad/IC-UBB/MixPix/CARAVEL_WRAPPER/MixPix/openlane/user_project_wrapper/runs/22_11_06_12_15/logs/routing/15-detailed.log
[ERROR]: Last 10 lines:
Units:                1000
Number of layers:     13
Number of macros:     443
Number of vias:       25
Number of viarulegen: 25

[INFO DRT-0150] Reading design.
[ERROR DRT-0305] Net zero_ of signal type GROUND is not routable by TritonRoute. Move to special nets.
Error: droute.tcl, 46 DRT-0305
child process exited abnormally

I check different slack channels, and I found this: https://open-source-silicon.slack.com/archives/C016H8WJMBR/p1659754025686099 proposed WA: https://open-source-silicon.slack.com/archives/C016H8WJMBR/p1662445019683969?thread_ts=1659754025.686099&cid=C016H8WJMBR I do make openlane to udapdate dependencies/openlane_src, rerun the flow and the problem still appears looks like a past bug; the WA mentioned in the thread solved the routing problem, but at the end of the flow there are LVS errors related to the fix. Is someone else having this problem with Caravel flow? The repo of the project is updated with the last changes here: https://github.com/HALxmont/MixPix

but at the end of the flow there are LVS errors related to the fix.

Is this your LVS result? If it is, can you post it?

Hi @Mitch Bailey here are some logs and more info about the LVS errors

Can you take a look as the synthesized layout? My initial guess is that you’re running at the top level using an option that doesn’t do standard cell rows so your

conb

cells are not being connected to power. Can you check the power connections to this cell in the top level? Maybe you have this in your config file (which is correct for the top level).

# The following is because there are no std cells in the example wrapper project.
set ::env(SYNTH_TOP_LEVEL) 0

Someone correct me if I’m wrong, but I don’t think it’s possible to synthesize ‘0’ and ‘1’ connections at the

user_project_wrapper

level.

user_project_wrapper config.tcl has

# The following is because there are no std cells in the example wrapper project.
set ::env(SYNTH_TOP_LEVEL) 1

Right. There are a lot of discussions about

SYNTH_TOP_LEVEL

on slack. Maybe you can figure out what to do from those. Sorry I couldn’t be more help.

Don’t worry, thanks for your help!