Hi , wanted some more information on logic analyz...
# caravelr
Ryan R
06/02/2022, 5:41 AMHi , wanted some more information on logic analyzer pins vs wishbone bus - Matt communicated that either the wishbone bus or the LA can be used at point of time. My query is when should we use the wishbone bus and when should we use the LA pins for controlling or sampling data from/to the user project ? Any advatnages or disadvantages ? Any detailed doc available ? Thanks
m
Matt Venn
06/02/2022, 6:38 AMwishbone requires some overhead on your design to implement a wishbone peripheral
Matt Venn
06/02/2022, 6:39 AMbut it's a standard, so for some people its very convenient, as they can reuse IP or use other people's IP and not have to make a new interface
Matt Venn
06/02/2022, 6:39 AMif you don't already have wishbone, and aren't making an SoC with lots of peripherals on a bus, then maybe stick with the LA, simpler and easier
r
Ryan R
06/02/2022, 6:56 AMThanks @Matt Venn - right now seems using LA seems viable.
Ryan R
06/02/2022, 6:57 AMBut do you have any idea about docs regarding those ? Like how to program the LA or wishbone ? Thanks
m
Matt Venn
06/02/2022, 7:01 AMcheck the tests that come with caravel_user_project
r
Ryan R
06/02/2022, 7:01 AMLet me check
m
Matt Venn
06/02/2022, 7:02 AMand here
Matt Venn
06/02/2022, 7:02 AMMatt Venn
06/02/2022, 7:03 AMalso some tests here: https://github.com/efabless/caravel_mgmt_soc_litex/tree/main/verilog/dv/tests-caravel
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