Hi, Iam actually trying to create a memory array in user space. I understand how the clk signal is assigned. I would like to connect data and address bus to gpio. But i have trouble understanding how mprj_io assignedment is done. I have modified the user_project as follows. Please help with how the mprj_io pin assignment is done. module user_proj_example #( parameter BITS = 32 )( `ifdef USE_POWER_PINS inout vccd1, // User area 1 1.8V supply inout vssd1, // User area 1 digital ground `endif // Wishbone Slave ports (WB MI A) input wb_clk_i, // IOs input [`MPRJ_IO_PADS-1:0] io_in, output [`MPRJ_IO_PADS-1:0] io_out, output [`MPRJ_IO_PADS-1:0] io_oeb, ); wire clk; assign clk= wb_clk_i; mem_array( .clk(clk), .data(mprj_io[7:0]), .addr(mprj_io[10:8), w_en(mprj_io[11]), r_en(mprj_io[12]), content(mprj_io[20:13]) ); endmodule module mem_array (input clk,input [7:0] data, input [2:0] addr, input w_en, input r_en, output reg [7:0] content); reg [7:0] mem [2:0]; always@(posedge clk) begin if(w_en==1 && r_en==0) mem[addr]=data; else if(r_en==1 && w_en==0) content=mem[addr]; end endmodule `default_nettype wire

1. You have syntax errors, fix them 2. The inputs are io_in and the outputs meed to be connected to io_out 3. If the pin is output then io_oeb is set to 0

Thanks. Where is actually mprj_io_pads defined?

So the top level verilog of caravel chip contains all connections. It contains the gpio modules which have three pins: in, out, output enable inverted. These pins are connected to the user area.