Hi, I was wondering if anyone else has had problems getting gl simulations to work properly. I've written some rtl tests that work correctly, but when I try the gl version they all fail. From looking at the simulation outputs I can see some activity on the wishbone bus, and then after ~300us everything gets an unknown value, which is before any requests get made to the user space wishbone port. Based on the address being read from it looks like the problem is either caused by reading past the end of data in the emulated flash, or due to the management core running a jump instruction. However, I tried the wb_port test from the example project without any issues, so I don't see how the problem can be with the management core. I would be grateful of any help, as I'm not really sure how to debug this further.

See if this thread helps you https://skywater-pdk.slack.com/archives/C017HPHCMEY/p1649629638190519

Thanks for the help. I added a pullup to mprj_io[3] as suggested in that thread, and it no long has the problem on the simulations I've rerun so far. Now I just have to deal with my simplest test taking ~2hours to simulate 6.5ms, and it still failed for some reason. At least now its probably due to something I've done. I don't suppose there are any tricks to running the GL simulations faster?

Couple of suggestion. 1. I see your project using default MPW-6 test case flows and waveform are dumped default . you can mask the dump or do selective dump or reduce the dump level from 0 to 1 -- ($dumpvars(0, peripheralsGPIO_tb); OR if your know how to hack the flow then you can add DUMP ON and OFF in run command 2. Instead of running all the test with caravel environment, you can create standalone test case to validate user project with driving test at wishbone interface. This atleast give some idea on issue is within user-project or not. 3. In Big design, gatelevel simulation are always tough to debug the failure, better option is to have selectively pick some block RTL file and GL netlist; This will be helps in quick debug

Ok thanks again, I'll try some of that and see if it helps. I'm can do most of my debugging in RTL simulations luckily, and then just running the GL simulations to make sure. Is there as way of passing the simulation type into the verilog, so that I can massively reduce the dump level when doing GL simulation, but still have it when doing RTL simulation?

Until MPW-4 there were easy way to pass the simulation variable, but MPW5 onward less user control on Makefile changes. You can refer my git repo: https://github.com/dineshannayya/riscduino_dcore , See if helps you. I tried to use the MPW-4 methodology and given simulation passing option like : make <test_case> SIM=<RTL/GL> DUMP=<ON/OFF> Example: RTL dump : make wb_port SIM=RTL DUMP=ON GL without dump : make wb_port SIM=GL DUMP=OFF Default mode is RTL and DUMP OFF, i.e make wb_port means make wb_port SIM=RTL DUMP=OFF

Ah, I see. I've not customised the makefiles yet, but that would be pretty easy to change. For now, I've found that it defines SIM/GL for rtl/gl simulations, and so I can make it only dump the top level when doing gl simulations.