Hey, I am (also) having trouble with the GL simula...
# caravelj
Jure Vreča
05/29/2022, 7:09 PMHey, I am (also) having trouble with the GL simulation of my design. Based upon previous post in this channel I added a pullup statement to my simulation, but this did not help. Did any of you had a similar experience? and do you have any tips on how to approach debugging? Another question is should I even bother with this? Or is RTL simulation enough? To recreate the issue you can try downloading: https://github.com/jurevreca12/rvj1-caravel-soc/tree/b37633479be1716f5e6a8edab3d1099baf5eea70 and running make verify-adding-gl . I am also attaching both the (succesfull) RTL simulation VCD and the unsuccessful GL simulation VCD.
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Charlie Smith
05/29/2022, 7:24 PMAs well as needing the pullup, another issue I had encountered was that floating inputs from mprj_io could cause unknown values to be propagated in GL simulations and mess everything up. My fix was to add a pulldown onto all pins that where not being used. It could be that you have a similar problem.
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Jure Vreča
05/29/2022, 8:33 PMI added a pull-up to all the mprj_io. But it did not fix it. Did you add pulldowns to others also?
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Charlie Smith
05/29/2022, 8:54 PMOh sorry, I just looked at my code and rather than the pullup, I just assigned all the unused pins to 0, I think that was so that I didn't need to have so many lines. No really sure what difference this would make, so maybe you've got a different problem.
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Jure Vreča
05/30/2022, 6:56 AMI tried also assigning all mprj_io to 0 and it didnt help..
Jure Vreča
05/30/2022, 1:35 PMSo I realized that my gatelevel must differ from the RTL. I've looked at the traces of instruction and data SRAM and I can see they differ at the point where my riscv core would have to write to d(ata)ram. I am not sure what to do now, why would this happen? I am attaching an image of a trace where at the exact same moment the RTL simulation writes 0xAB610000 to DRAM (for my simulation this signals an susccessfull end), but the GL simulation does nothing.
Jure Vreča
05/30/2022, 1:35 PMimage.png
Jure Vreča
05/31/2022, 6:39 AMIf anyone has a similar problem, I was able to solve this. The reason this was happening is because in my code somewhere I had a reg that was included in two always blocks. I picked up on this by using verilator as a linting tool.