Does anyone have any examples or information about how to either run the SPI in quad mode or transfer instructions to RAM and execute from there? I'm running some simulations for a test design and have found that my biggest bottleneck is the speed at which the litex core can write to and read from the user project area over the wishbone interface. I searched on here and found examples of both but it seems that the quad SPI functionality may no longer be present in the litex, and the example code for loading instructions into the RAM doesn't work in simulation. Any advice is appreciated.

Yes. (1) Running in quad mode: See the testbench

qspi

in

verilog/dv/caravel/mgmt_soc/

. But beware that the SoC is currently defined as a VexRISC, and their SPI flash controller does not handle quad mode. (2) Running from SRAM: See the testbench

sram_exec

in the same

verilog/dv/caravel/mgmt_soc/

. This testbench was transferred to the VexRISC (and I assume it works) so you can find it in both the old caravel repository from the MPW-one or MPW-two tags, or in the caravel_mgmt_soc_litex repository.