Hi, I have the following warning and I don't know if it's important and how to solve it. The document doesn't talk about slew violations. The warning:

[WARNING]: There are max slew violations in the design at the typical corner. Please refer to /project/openlane/core/runs/core/reports/routing/25-spef_extraction_sta.slew.rpt

Hi @User I had the same issue, but have not found the solution. I suppose the developers are working on that. There are more people with this problem @User

And do you know if this warning is something very important to take care about it that may prevents the chip to work?

it is the violation of the maximum transistion tim of the clock

I changed the period from 50 to 75 and I still have the warning. But the the violations numbers changed from 0.9 to 0.5

Actually what you did You have lovered the frequency, give it a try for 40 ns of period

I tried even with 20 and I get the same warning

@User the lower the period the most likely You got error

@User would also be good to get some followup on this one