Hi, I have a problem in my design. It doesn't matter how bigger I do the clock (from 50 to 100) that I always get:

[ERROR]: There are hold violations in the design at the typical corner. Please refer to /project/openlane/core/runs/core/reports/routing/25-spef_extraction_sta.min.rpt.

Looking into that document I always get the same range of violation from 0.05 to 0.17 even with the same period and configuration. I have read the document and tried:

set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) "30"

from 30 to 90

set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) "30"

from 30 to 90

set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1

set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) 1

What can I do to fix this small hold violations? Am I using properly those variables? Should I try another variables?

You might try increasing PL_RESIZER_HOLD_SLACK_MARGIN

Hi, thanks that variable and the same one for GLB seems that fixed my problem