Matt Venn
12/28/2022, 9:56 AMMatt Venn
12/28/2022, 9:57 AMMatt Venn
12/28/2022, 9:57 AMTobias Strauch
12/28/2022, 10:36 AMAndras Tantos
03/01/2023, 7:16 PMAndras Tantos
03/01/2023, 7:16 PMAndras Tantos
03/01/2023, 7:17 PMDerek Hines-Mohrman
03/04/2023, 1:10 AMmp_serializer_top
, which contains the instance serializer_inst
, which has a pin dest_clk_i
.
I have tried the following commands:
get_pins "serializer_inst/dest_clk_i"
get_pins "serializer_inst.dest_clk_i"
get_pins -hsc "/" "serializer_inst/dest_clk_i"
get_pins "\\serializer_inst/dest_clk_i"
get_pins "mp_serializer_top/serializer_inst/dest_clk_i"
get_pins "\\mp_serializer_top/serializer_inst/dest_clk_i"
However, they all fail (saying pin cannot be found)
Also, when I try to see a list of all pins with get_pins *
, it returns:
_9031d90700000000_p_Pin _2033d90700000000_p_Pin _7033d90700000000_p_Pin ...
as if the design has been flatted and all original names removed. So I don't even have an example of what a correct pin name is.
When looking at SDC scripts posted by others on this channel, it seems like accessing pins in this way is commonly done... What am I missing?
Any help appreciated, thank you!Tobias Strauch
03/14/2023, 4:53 PMEric Smith
03/24/2023, 4:53 PMEric Smith
03/24/2023, 4:53 PMEric Smith
03/24/2023, 5:08 PMread_liberty example1_slow.lib
read_verilog example1.v
link_design top
read_sdf example1.sdf
read_spef example1.spef
set_data_check -fall_from X1.Y -to X1.A -hold $H
report_checks
And it will measure the delay and compare against the hold requirement. This way I can be sure is at least $H long, and also get the prediction from the log.Eric Smith
03/24/2023, 5:09 PMEric Smith
03/24/2023, 6:12 PMEric Smith
03/27/2023, 4:04 PMread_liberty example1_slow.lib
read_verilog example1.v
link_design top
read_sdf example1.sdf
read_spef example1.spef
report_checks -unconstrained -format end -through {X1/Y} -to {X1/A}
Does that seems like a reasonable way to do it?
@Vijayan Krishnan I’ll try to make a small test case that demonstrates the report_annotated_delay issue.Xiaochen Ni
04/20/2023, 5:35 PMMatt Venn
06/05/2023, 4:22 PMSoumil Jain
06/21/2023, 7:26 AMIndira Iyer
06/27/2023, 9:29 PMMariam Rakka
07/05/2023, 1:50 PMtnt
08/01/2023, 5:55 PMWarning: There are 9 unclocked register/latch pins
and then it lists them. One of them is listed as top_I.ctrl_I/genblk1[1].cnt_bit_I.cell0_I/CLK
. It's a pin inside an instance of the current design. top_I.ctrl_I
is the name ofthe instance and inside of it there is a FF instance genblk1[1].cnt_bit_I.cell0_I
that has a pin named CLK
. But no matter WTF I do I cannot for the life of me make a [get_pins ...]
command match it ...tnt
08/01/2023, 7:35 PMmax_delay
constrainst (for comb path) between a port and an internal pin (that goes to a black box macro) but it doesn't see to find any path ... is that not supported ?tnt
08/01/2023, 9:04 PMtnt
08/02/2023, 6:21 PMtnt
08/02/2023, 6:22 PM% get_nets -of_objects [get_pins mux1_I/cell0_I/Z]
_90596fdd3a560000_p_Net
% get_nets -of_objects [get_pins mux1_I/out]
_60586fdd3a560000_p_Net
They're not the same net ... even though realistically they should be !
% find_timing_path -from [all_inputs] -to [get_pins mux1_I/cell0_I/Z]
_207070dd3a560000_p_PathEnd
% find_timing_path -from [all_inputs] -to [get_pins mux1_I/out]
%
And as you see it finds timing path to the first one ... but not the second one ...tnt
08/02/2023, 6:24 PMVinayaka Karthik
08/12/2023, 3:22 PMMohammed Fayiz Ferosh
10/23/2023, 2:06 AMtnt
10/25/2023, 10:57 AMFanout Cap Slew Delay Time Description
---------------------------------------------------------------------------------------------
[...]
0.073909 0.000168 0.253725 ^ block[12].genblk1.tbuf_spine_ow_I[23].genblk1.cell0_I/A (sky130_fd_sc_hd__ebufn_8)
1 0.289250 1.130828 0.881752 1.135478 ^ block[12].genblk1.tbuf_spine_ow_I[23].genblk1.cell0_I/Z (sky130_fd_sc_hd__ebufn_8)
block[0].genblk1.tbuf_spine_ow_I[23].z (net)
3.406518 0.065144 1.200622 ^ buf_spine_ow_I[23].genblk1.cell0_I/A (sky130_fd_sc_hd__buf_2)
1 0.006288 0.113416 0.422576 1.623198 ^ buf_spine_ow_I[23].genblk1.cell0_I/X (sky130_fd_sc_hd__buf_2)
[...]
The output slew at the output of that ebufn_8
is ~ 1.13 ns. But then at the next line the input slew at the buf_2
is 3.4 ns. ( And no, there is no big resistive net or anything, looking at spice sims of that net, the output slew of the buffer is pretty much the same as the input slew of the receiver ).
But on the same net I also have a very weak ebufn_1
( in another path). And if I remove that ebufn_1
(which is not involved at all in the path being reported here), then the 3.4 ns disappears and instead it's like 1.14 ns which is what I'd expect.teolinhka
11/04/2023, 3:30 PM