It looks like our synthesized clock tree on our MPW2 design is horrible:

report_clock_skew
Clock io_in[17]
Latency      CRPR       Skew
_2896_/CLK ^
  20.60
_3240_/CLK ^
   5.85     -3.49      11.26

Is there any way to get a parasitic-aware clock tree generated? This results in timing problems:

Startpoint: _3239_ (rising edge-triggered flip-flop clocked by io_in[17])
Endpoint: _3240_ (rising edge-triggered flip-flop clocked by io_in[17])
Path Group: io_in[17]
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.00    0.00    0.00   clock io_in[17] (rise edge)
                          6.77    6.77   clock network delay (propagated)
                  0.04    0.00    6.77 ^ _3239_/CLK (sky130_fd_sc_hd__dfxtp_2)
                  0.20    0.32    7.09 ^ _3239_/Q (sky130_fd_sc_hd__dfxtp_2)
     5    0.04                           la_data_out[33] (net)
                  0.20    0.00    7.09 ^ _2637_/A1 (sky130_fd_sc_hd__mux2_1)
                  0.03    0.10    7.20 ^ _2637_/X (sky130_fd_sc_hd__mux2_1)
     2    0.00                           _0039_ (net)
                  0.03    0.00    7.20 ^ hold394/A (sky130_fd_sc_hd__dlygate4sd3_1)
                  0.06    0.39    7.59 ^ hold394/X (sky130_fd_sc_hd__dlygate4sd3_1)
     2    0.01                           net394 (net)
                  0.06    0.00    7.59 ^ _1380_/A1 (sky130_fd_sc_hd__o221a_2)
                  0.03    0.10    7.69 ^ _1380_/X (sky130_fd_sc_hd__o221a_2)
     2    0.00                           _0782_ (net)
                  0.03    0.00    7.69 ^ hold393/A (sky130_fd_sc_hd__dlygate4sd3_1)
                  0.05    0.38    8.07 ^ hold393/X (sky130_fd_sc_hd__dlygate4sd3_1)
     2    0.00                           net393 (net)
                  0.05    0.00    8.07 ^ _3240_/D (sky130_fd_sc_hd__dfxtp_2)
                                  8.07   data arrival time

                  0.00    0.00    0.00   clock io_in[17] (rise edge)
                         16.23   16.23   clock network delay (propagated)
                         -3.49   12.74   clock reconvergence pessimism
                                 12.74 ^ _3240_/CLK (sky130_fd_sc_hd__dfxtp_2)
                         -0.02   12.72   library hold time
                                 12.72   data required time
-----------------------------------------------------------------------------
                                 12.72   data required time
                                 -8.07   data arrival time
-----------------------------------------------------------------------------
                                 -4.66   slack (VIOLATED)

Hi Matt, can you share a github link. We are looking for designs failing hold. @User and @User

I thinknif it runs smoothly then you don't have to. This is using tools tagged for mpw2 right? Or maybe mpw3?

@User this is what the project installed: tag: 2021.09.19_20.25.16

Thanks @User. We will try it and ask if there are any issues running it on our end.

@User @User Hi. I am trying to run the MPW2 design by

make openlane

under openlane folder, but got this error. Do you have any ideas what is going on? I am not sure if I am on the right way.

That error means it was unable to download the docker image, I think.

What is the right way to run the design,

make all

? I changed the tag manually, and then I got this error.

You can do a docker pull with the correct name. I'm not sure why it failed before

@User have you tried this?