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I have a doubt about RCX/STA on the openlane flow:
I have a design that uses a previously built macro, which I include in the project using its .LEF and .GDS
If I understand correctly rcx and sta uses .LEF/.DEF files to run (not the final GDS), so timing analysis is not using the detailed version of my macro?
I have already done the STA on my macro, but I'm wondering if it's enough to pass timings on both projects separately

interesting question. I would have thought it was enough, because it's not like the standard cells are simulated - the timing information is used instead, so only the names of the cells would be needed.

doing timing analysis with spice would be far too slow

You need to go for hierarchical timing. Not sure if it's supported in openSta

There is no automatic way in opensta to make a liberty model for a netlist and use it one level up. This is doable but has not been implemented yet. What most sta users do, even proprietary tool users, is to run sta signoff flat even if the construction flow is done with hierarchy. I think you should make an sta run that sees the detailed netlist for the top and inside the block. For extraction, you can run openrcx separately and load each (the top and the block spef)  into opensta. The read spef command can be scoped to an instance path.

<@U0172QZ342D> the problem is that the macro's .LEF doesn't have much information, just the PINS, not wires or standard cells.

<@U01AX8X5N58> I've made some tests but I couldn't assign the spef of the macro to the instance yet, because after loading the two verilog files there's no instance on openroad representing the top module of the macro (it gets replaced by its contents)
Aside from that, by having the full hierarchy network, the STA runs on the whole chip. In the case of the nets with no SPEF correlation, the process uses some estimates, right? Is not as good but still useful?

I wouldn't trust the estimates. There should be a command like current instance or an option to read spef that take an instance path to scope the spef to. If you cant find it in the pdf manual in the sta directory I will ask the author.

I've found the command  `read_spef [file] -path [instance]` but the issue I'm having is that I can't find the instance I should scope the spef to.
If I only load and link the top verilog there is a `somemodules.marco_instance` on the OR db (that it would be what I think I should scope the spef to).
The problem is that when I load the top and macro verilog files and link them I don't have a `somemodules.marco_instance` anymore. I just have all the content instances `somemodules.macro_instance/outputX, somemodules.macro_instance/inputX, etc`
Maybe there's an order on the commands I need to use or I missing something (I'm really new to all this)

Ok. I found a problem. I was runnig all this in `openroad` as it was what the `make rcx-xxxxx` on caravel uses.
But running it on `sta` seem to be working fine. I can scope the spef to my `somemodules.macro_instance`