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I am bashing my head against the wall to get this ...
# timing-closure
k
I am bashing my head against the wall to get this .. work. I've followed the instructions mentioned above and I keep getting:
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[INFO ODB-0225]     Created 1 library cells
[INFO ODB-0226] Finished LEF file:  ./lef/wrapper.lef
[WARNING ORD-1011] LEF master wrapper_fibonacci has no liberty cell.
[WARNING ORD-1011] LEF master wrapper_sha1 has no liberty cell.
set ::env(CLOCK_PERIOD) 20
set ::env(CLOCK_PORT) wb_clk_i
set ::env(IO_PCT) 0.2
set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_1"
set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
set ::env(SYNTH_CAP_LOAD) "33.5"
set ::env(SYNTH_MAX_FANOUT) "4"
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set_propagated_clock [get_clocks $::env(CLOCK_PORT)]
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 4.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 4.0
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.0335
set_load  $cap_load [all_outputs]
No paths found.
No paths found? But if I grep for wb_clk_i I can see it in lef/* and def/*
log.txt
m
What is the output of create_clock in the log?
k
@User what about defining the ClockNet ?
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set ::env(CLOCK_PORT) "wb_clk_i"
set ::env(CLOCK_NET) "wb_clk_i"
k
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set ::env(CLOCK_PERIOD) 20
set ::env(CLOCK_PORT) "wb_clk_i"
set ::env(CLOCK_NET) "wb_clk_i"
set ::env(IO_PCT) 0.2
set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_1"
set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
set ::env(SYNTH_CAP_LOAD) "33.5"
set ::env(SYNTH_MAX_FANOUT) "4"
puts "Before"
Before
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
puts "After"
After
@User Nothing 😞
m
That should be good
Clock net is what to run CTS on, not for STA
k
what about specifying the output manually instead of: set_load $cap_load [all_outputs]
k
Hmm, so I did this to find that:
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set clock_lists [get_clocks $::env(CLOCK_PORT)]
foreach clock_asgn $clock_lists {
     set node_name [lindex $clock_asgn 0]
     set clock_setting_name [lindex $clock_asgn 1]
     if { $node_name == "" } {
          puts "No node uses the clock \"$clock_setting_name\""
     } elseif {$clock_setting_name == ""} {
          puts "The node \"$node_name\" uses an undefined clock setting";
     } else {
          puts "The node \"$node_name\" uses the clock \"$clock_setting_name\""
     }
}
The node "_d0d9fa0400000000_p_Clock" uses an undefined clock setting
k
BTW, what are the default units of capacitance in OpenSTA ?
The scripts defines this set ::env(SYNTH_CAP_LOAD) "33.5" however after it reports that [INFO]: Setting load to: 0.0335 ?
k
Yup. There is a / 1000
k
seems that the dafault is pF
going back to Your log I do not think I can help You with that. I suppose @User could, he is an expert is STA
t
Units in opensta follows the commercial tool convention that the units are set based on the first liberty file loaded units.
k
Hi @User, thank You for Your replay. I ran the report_units command, so no doubt about the units anymore
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report_units
 time 1ns
 capacitance 1pF
 resistance 1kohm
 voltage 1v
 current 1mA
 power 1nW
 distance 1um
in this thread @User has an issue with some missing paths
v
@User is your issue got fixed or share your runs/.../config.tcl
@User set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_1" change this variable by setting set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_2" in config.tcl and run the flow and let me know
k
@User hi, in fact this issu is not mine, I was trying to help here. BTW what is the default driving cell in caravel harness? I mean if my user project example receives signals, those signals are driven by sky130_fd_sc_hd__inv_1? Time agoo I spoke with @User and he indicated me that ihe default one is sky130_fd_sc_hd__inv_8 and fot the signals coming from GPIO modules there was other cell named sky130_fd_sc_hd__einvp_8.
v
As per given log user using sky130_fd_sc_hd__inv_1. I've seen other user reported like no paths found. Maybe same workaround will work for you as well.
k
My design works well with sky130_fd_sc_hd__inv_8, I was worried about STA results and timing in general
t
No paths found means that report_checks did not find any constrained timing paths. I expect the problem is with the sdc.
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