Hi, question about the full chip simulation: my project for MPW5 tapeout is a purely analog VCO without digital RTL, just analog inputs (Vctrl voltage into the VCO), as well as 1.8V digital inputs directly to the analog IP (to turn on/off some switches), then a digital output (a frequency divided-down version of the VCO output). My question is, do I need to run any full chip sim in this case? I see mentioned in the Caravel guides that one should run a full chip simulation to check your design is correctly integrated into Caravel, but my project is only analog and no RTL so, do I need to run any kind of full chip sim to verify connectivity of my IP into the Caravel container? Thanks

Yes, a full-chip simulation is strongly encouraged. You can make a simple RTL verilog of your analog. See

verilog/rtl/example_por.v

in the caravel_user_project_analog repository. The behavior doesn't need to even roughly match the analog, like it does in that example. If it just receives inputs on pins you believe to be inputs, and then generates some output response on pins you believe to be outputs, then you have some meaningful indication that your project is wired up correctly.