In the caravel user project, while going through the user example project verilog code, it can be seen that the 'BITS' was defined. But nowhere else 'MPRJ_IO_PADS' was defined. I was trying to generate the RTL schematic of user wrapper and user project separately. any help?

1. Its defined in defines.v 2. What schematic? What does it mean to generate the schematic separately. I dont quite understand what you mean

i was trying to generate the rtl schematic just to see how user project is connected to user wrapper. Thought it would be an easy way to visualize what is written in the code. Between, i have been searching for the defines.v file which was not available in the rtl folder or in the verilog folder. any help?

It's in the caravel repo. From your

config.tcl

file

set ::env(VERILOG_FILES) "\
        $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
        $script_dir/../../verilog/rtl/user_proj_example.v"