@User: The management SoC is set up so that it protects against input signals from the user project being unconnected (left open). So all signals coming from the user project to the management SoC need to be enabled by the program running on the management SoC, which tells the management SoC that the signal is valid and there is something connected to it on the user side. Obviously this needs to be set on a per-user-project basis. The management SoC will not be able to communicate with the user project through wishbone until this enable bit is set. However, all outgoing signals from the management SoC to the user project are unaffected by this, so as Matt said, the wishbone clock and reset are always present at the user project input.

hold on, what is the enable for inputs coming to the SoC?

This is only for the signals from the user project area to the SoC, so it's only on the logic analyzer inputs (

la_iena[]

are the enable signals), and the wishbone data (in the direction from user to management) and

ack

signal. The data and

ack

are both enabled by the single "wishbone enable" bit. The logic analyzer input enables are individually controlled (one bit each).

thanks