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Where can I find the up to date information on interrupt connections in Caravel to the VexRisc CPU? <https://caravel-harness.readthedocs.io/en/latest/irq.html|This> page still contains instructions for the Pico CPU.

Found some documentation <https://github.com/efabless/caravel_mgmt_soc_litex/tree/main/docs/generated|here>. Is there a more human readable version somewhere with some high level context?

there is some info in the faq: <https://docs.google.com/document/d/1Y7LuP_0dJ_vmD8G_Twc6qc97fj7aW5pRV5nAjN2oOUk/edit#heading=h.dabsoa4nkp71>

I tried to put together this: <https://docs.google.com/document/d/19At2TtVZSNaKqbcPY6uSJcvKjPAxnRGONdAwTsjWI9A/edit#heading=h.iwo6vjkxhgh8> to explain the difference between the pico core and the new one

<@U02TGPV63FA> check the link again, I pasted the wrong one

&gt; <@U02TGPV63FA> check the link again, I pasted the wrong one
Thanks! I have gone through that document already. My main question is (without understanding RISCV interrupt architecture), how do I enable the user interrupts on the CPU? There appears to be a register you have to write to enable. Perhaps a simple example would have been nice. I'll try to dig in further myself otherwise.

yes, best place for that I would think would be the tests

try this: <https://github.com/efabless/caravel_mgmt_soc_litex/tree/main/verilog/dv/tests-standalone/irq>

I'm also interested in getting the docs improved so if you come up with an example please let me know

Sure! For mpw-6 or later, it would be good to add a user project interrupt pin test. Maybe connect the counter output to the user interrupts? For overflow/underflow conditions and a C test to show the usage of handler?
This is what I'm going to do now to test our system as a start.

if you want to make a PR on that repo, it would be highly appreciated!

we are working on getting more coverage on the tests