Hi everyone, I am working on a mixed signal chip a...
# caravela
Ankur Sharma
04/04/2022, 10:37 PMHi everyone, I am working on a mixed signal chip and one of the first steps in integration with caravel is to have the analog blocks as blackbox and linking them with the pins. I created a simple inverter in magic, added pins for vccd1(power), vssd1(ground), inp, out. I took the gds and lef files from there and placed in the /gds and /lef of caravel_example. I made the changes in the tcl file appropriately. When building user_proj_wrapper, I get the error at the lvs stage. The pins vccd1 and vssd1 are mismatched. Here are the inverter.v, user_proj_wrapper.v, config.tcl file and the lvs log file. Please point me to what needs to change in the design. Thanks!
m
Mitch Bailey
04/04/2022, 11:04 PMCan you share your extracted netlist?
find user_project_wrapper -name '*.spice'a
Ankur Sharma
04/04/2022, 11:44 PM Copy code
* NGSPICE file created from user_project_wrapper.ext - technology: sky130A * Black-box entry subcircuit for inverter abstract view .subckt inverter inp out vccd1 vssd1 .ends .subckt user_project_wrapper analog_io[0] analog_io[10] analog_io[11] analog_io[12] + analog_io[13] analog_io[14] analog_io[15] analog_io[16] analog_io[17] analog_io[18] + analog_io[19] analog_io[1] analog_io[20] analog_io[21] analog_io[22] analog_io[23] + analog_io[24] analog_io[25] analog_io[26] analog_io[27] analog_io[28] analog_io[2] + analog_io[3] analog_io[4] analog_io[5] analog_io[6] analog_io[7] analog_io[8] analog_io[9] + vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 Xmprj analog_io[0] analog_io[1] mprj/vccd1 mprj/vssd1 inverter .endsm
Mitch Bailey
04/05/2022, 12:57 AMYou can see that the power to the inverter is not connected at the
user_project_wrappermprj/vccd1mprj/vssd1👍 1
a
Ankur Sharma
04/05/2022, 2:27 AMI tried to take a second look at the design and all the verilog files as well. I don't see any difference in the way that I am connecting the inp/out pins and the power pins. Do I need to take some extra steps when linking the power pins? I have added the lef file for the inverter as well in the same folder if you want to take a look at that.
m
Mitch Bailey
04/05/2022, 2:33 AMDoes this thread help? https://skywater-pdk.slack.com/archives/C016H8WJMBR/p1647891784565939
a
Ankur Sharma
04/05/2022, 4:33 PMUnfortunately, it didn't work. This seems to be the same issue as https://skywater-pdk.slack.com/archives/C016H8WJMBR/p1648103815845739. I tried the following links as well:
1. https://openlane-docs.readthedocs.io/en/rtd-develop/doc/advanced_power_grid_control.html
2. https://github.com/efabless/caravel/blob/main/openlane/user_project_wrapper/fixed_wrapper_cfgs.tcl
3. https://github.com/wokwi/wrapped_skullfet/blob/main/config.tcl
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