All of the other precheck scripts were fairly simp...
# shuttle-precheckw
Will R
05/12/2022, 2:41 PMAll of the other precheck scripts were fairly simple to work through, and those are the only two issues that we are still encountering. Thank you for creating an easy-to-use design check for the Caravel shuttle program!
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Matt Venn
05/12/2022, 8:27 PMCan you move your macro a bit further away?
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Will R
05/12/2022, 8:56 PMThe macro is actually a 0.9x0.6mm tile near the center of the design area, but we do have fill/etc cells on the top level.
Will R
05/12/2022, 8:59 PMWe're using the caravel_user_project .def file as a floorplan:
https://github.com/efabless/caravel_user_project/blob/main/def/user_project_wrapper.def
Will R
05/13/2022, 1:29 AMI think that I was wrong about the purpose of the "not-over drawing" error message. It seems to be checking for metal layer overlaps, not boundary overlaps. We have some floating pins, and the lack of metal3 70/20 "drawing" layers over the metal3 70/16 "pin" layers (and similar for metal2) seems to be what is triggering these errors.
Will R
05/13/2022, 12:47 PMHm, connecting the floating pins didn't help. I'm a bit stumped as to what these "Pin Label Purposes Overlapping Drawing" checks are looking for.
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Mitch Bailey
05/16/2022, 6:47 AMOne of the previous problems was that LVS treated pin, label, and drawing layers as connected layers, but the actual masks were only created from drawing layers. Thus LVS would pass, but the actual circuit might be disconnected. To prevent this, I believe DRC rules were added requiring pin and label layers to be completely inside drawing layers. So if you have pins or labels without drawing layers, you should get an error.
Mitch Bailey
05/16/2022, 6:49 AMEssentially a repeat of @User's answer.
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Will R
05/16/2022, 4:29 PMThat makes sense, thank you! It also explains why covering the pins with a 'drawing' layer causes the check to pass.
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Wajeh ul hasan
05/16/2022, 5:30 PMDid you manually draw the layer ? @User
Wajeh ul hasan
05/16/2022, 5:32 PMI am more interested in knowing why it missed the layer in the first place. Did you get this error on every pin or any specific pin? @User
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Will R
05/16/2022, 5:45 PMYes, I got the error with every pin, so I ended up modifying the DEF file after detailed routing. Adding tracks over the pins seems to satisfy the check. There are probably better ways to do this, but you can create a track on the 'drawing' data type by adding lines to the SPECIALNETS section, like:
- [net_name] ( PIN [net_name] ) + USE SIGNAL+ ROUTED [layer] [track_width] + SHAPE STRIPE ( [track_x1] [track_y1] ) ( [track_x2] [track_y2] )NEW [layer] [track_width] + SHAPE STRIPE ( [track_x1] [track_y1] ) ( [track_x2] [track_y2] ) ;