Found the reason for this issue. Was copying wrong file i.e.

xschem/user_analog_project_wrapper.spice

to

netgen

folder. It should have been

mag/user_analog_project_wrapper.spice

file instead.

@Tim Edwards I am getting XOR check errors during precheck as metal over few io_analog[ ] pad area is over drawn. Does this issue critical for pre-check or can be ignored ?

XOR gds generated from pre-check shown in attached screenshot above.

@Mitch Bailey @Tim Edwards Hi I am getting few checks failed while submitting the gds to MPW precheck Out of 12 check 2 failed 1. NETLIST CONSISTENCY CHECK FAILED 2. KLAYOUT FEOL CHECK FAILED : can you please help what is the fix required to do log files for the reference

logs.zip

{{OEB CHECK FAILED}} The design, user_analog_project_wrapper, has OEB violations.

Can we submit the design even if we are facing this issue?

Hi While using GPIO as analog pins what should be the condition for io_oeb and in which file we need to specify the io_oeb condition.

@Mitch Bailey I am facing FEOL , BEOL errors in local precheck and trying to rectify them. Is there any way in local precheck to run only these specific checks and skip other checks in order to save time.

@Saranya P U has left the channel

while we running caravel_user_project_analog we got some errors in precheck. cvc.oeb.log is attached here for reference. How i rectify this error.

while running precheck for analog design got consistency error.. how this can be rectified

@Tim Edwards @Matthew Guthaus @jeffdi I am facing 19 BEOL DRC violation inside the 2KB SRAM (sky130_sram_2kbyte_1rw1r_32x512_8). This memory picked from PDK. Look like new/update DRC rule is creating issue. Is there updated any SRAM available for latest PDK? All the Violation are related to : via3.2 : min. via3 spacing : 0.2um

hi @Mitch Bailey @Tim Edwards what does error fail OEB check means in precheck?

image.png

For users of the sky130B process. There appears to be an issue where magic drc for precheck fails and zero errors are being reported. There may also be an issue where Openlane runs and the drc log file shows errors, but none are reported in the flow. Recommend manually checking the

<step>-drc.log

.

When will the Efabless MPW Precheck be updated? I started it overnight, but it's currently stuck at the OEB step because I'm using the foundry provided SRAM for GF180 and the version of Magic used for the precheck is smaller than v8.3.442. Locally the test passed, there I updated Magic manually for the Docker image.

Noticing some strange behaviour from Openlane regarding Klayout FEOL layers. We hardened a digital-only macro (

TOP_digital

), then instantiated this into a mixed signal design which gets incorporated into the user_project_wrapper. The strange behaviours are these: 1. Openlane appears to have generated FEOL DRCs during the hardening process of

TOP_digital

. All of the FEOL DRCs are associated with this macro which Openlane previously made. 2. Whats more bizzare, is that the precheck for user_project_wrapper, sometimes it flags up these DRCs, and sometimes it doesn't. Because

TOP_digital

doesn't get re-hardened or regenerated during the user_project_wrapper build, I don't understand where this inconsistency is coming from.

From yesterday's pre-check:

image.png

This mornings:

All of those DRCs are from Openlane's

TOP_digital

macro, to which we have made no changes in the last few days:

@Mitch Bailey Hi David, Hi Tim @Tim Edwards @jeffdi I have disconnected all the gpio in connections and even then I am seeing OEB fails. attached the log files for the reference. Can you please guide to fix this issue. This issue was not found in the "initial_submit_04" run submitted re-used this database and fixed the FEOL error and re-submitted, now OEB errors are araised. Any update done in the submission or anything

@Tim Edwards @Mitch Bailey @jeffdi for the tapeout check I am getting this error.I don't think its my design related issue.All checks seem to pass

@Mitch Bailey @Tim Edwards

Is there any restrictions diff_fill cannot overlap on the Li_drawing layer? Slack Conversation

Currently new to this and I am having errors on OEB precheck: I am doing some testcase run to familiarize myself but got hit with this roadblock. I have assigned this pin to '0' so I am not sure why it is being flagged.

any help?

Hi, @Mitch Bailey I am running local pre-checks on my design. I am getting error in xor checks. I am using all the default values for PDN generation and IO pins as per the tag gfmpw-1b and am building the design directly in the wrapper not importing it as a macro. I wanted to ask if reducing the pdn spacing will make a difference in the said issue. Also if I reduce he core area and keep the die area same will it make the xor checks likely to pass. Is changing the core area likely to cause issue in tapeout job?

@Tim Edwards @Mitch Bailey I get this error while doing mpw check on platform

Hi, I am new to efabless tape out process and the use of open source tools. I have designed a two stage opamp to understand the design and tape out process for analog circuits. While running precheck locally, the GPIO-Defines check is failing. I have edited the user_defines.v file as suggested but the error is still present. Please see the attached user_define.v file and precheck log. Moreover, the precheck is not running LVS. The caravel was initially installed for digital designs (MPW8) with user_project_wrapper but I cloned an user_analog_project_wrapper and followed the steps with the old CARAVEL_ROOT path. Is that creating the issue? Please help me with the issue.