vks
11/01/2023, 4:48 PMxschem/user_analog_project_wrapper.spice
to netgen
folder. It should have been mag/user_analog_project_wrapper.spice
file instead.vks
11/01/2023, 6:07 PMvks
11/01/2023, 6:07 PMsamarth jain
11/02/2023, 2:11 PMsamarth jain
11/02/2023, 2:13 PMMilan P Manoj
11/03/2023, 7:19 AM{{OEB CHECK FAILED}} The design, user_analog_project_wrapper, has OEB violations.
Can we submit the design even if we are facing this issue?Saranya P U
11/03/2023, 9:06 AMvks
11/04/2023, 8:09 AMSaranya P U
11/04/2023, 10:48 AMSaranya P U
11/06/2023, 5:16 AMLEEJA J
11/08/2023, 9:55 AMDinesh A
11/08/2023, 6:02 PMsamarth jain
11/09/2023, 12:30 AMsamarth jain
11/09/2023, 12:32 AMMitch Bailey
11/09/2023, 1:57 AM<step>-drc.log
.Leo Moser
11/09/2023, 5:26 AMEllen Wood
11/09/2023, 10:41 AMTOP_digital
), then instantiated this into a mixed signal design which gets incorporated into the user_project_wrapper. The strange behaviours are these:
1. Openlane appears to have generated FEOL DRCs during the hardening process of TOP_digital
. All of the FEOL DRCs are associated with this macro which Openlane previously made.
2. Whats more bizzare, is that the precheck for user_project_wrapper, sometimes it flags up these DRCs, and sometimes it doesn't. Because TOP_digital
doesn't get re-hardened or regenerated during the user_project_wrapper build, I don't understand where this inconsistency is coming from.Ellen Wood
11/09/2023, 10:43 AMEllen Wood
11/09/2023, 10:43 AMEllen Wood
11/09/2023, 10:44 AMEllen Wood
11/09/2023, 10:45 AMTOP_digital
macro, to which we have made no changes in the last few days:samarth jain
11/09/2023, 12:26 PMsamarth jain
11/13/2023, 4:30 AMsamarth jain
11/13/2023, 4:19 PMsamarth jain
11/13/2023, 4:19 PMJian Ramark Maranan
11/17/2023, 6:39 AMSANEE AMAN 2233 Batch,PES University
11/18/2023, 9:12 AMAbdul Moiz Sheikh
11/21/2023, 6:15 PMsamarth jain
11/22/2023, 2:55 PMNaina
11/23/2023, 10:03 PM