Hi, everyone - we are seeing a somewhat confusing ...
# shuttle-precheckw
Will R
05/12/2022, 2:04 PMHi, everyone - we are seeing a somewhat confusing failure in the mpw_precheck consistency check. It looks like the check is expecting our gate-level netlist to contain modules for the vias which connect our standard cell rails to the PDN. Has anyone seen an error like this before? It looks like the core macro and top-level cells are all connected properly, it's just the vias that cause issues:
LAYOUT CHECK FAILED: The GDS layout for user_project_wrapper doesn't match the provided structural netlist. Mismatching modules are: ['VIA_L1M1_PR_MR' 'VIA_M1M2_PR' 'VIA_M2M3_PR' 'VIA_M3M4_PR''VIA_via2_3_3100_480_1_9_320_320' 'VIA_via3_4_3100_480_1_7_400_400''VIA_via4_3100x3100' 'VIA_via4_5_3100_480_1_7_400_400']Will R
05/12/2022, 10:12 PMI was able to fix the consistency check by adding via definitions to the gate-level netlist which OpenROAD outputs, but I'm not sure if that's the best solution:
module user_project_wrapper ([...snip...]VIA_L1M1_PR_MR(vssd1);VIA_L1M1_PR_MR(vccd1);VIA_M1M2_PR(vssd1);VIA_M1M2_PR(vccd1);VIA_M2M3_PR(vssd1);VIA_M2M3_PR(vccd1);VIA_M3M4_PR(vssd1);VIA_M3M4_PR(vccd1);VIA_via2_3_3100_480_1_9_320_320(vssd1);VIA_via2_3_3100_480_1_9_320_320(vccd1);VIA_via3_4_3100_480_1_7_400_400(vssd1);VIA_via3_4_3100_480_1_7_400_400(vccd1);VIA_via4_3100x3100(vssd1);VIA_via4_3100x3100(vccd1);VIA_via4_5_3100_480_1_7_400_400(vssd1);VIA_via4_5_3100_480_1_7_400_400(vccd1);endmodule