Hello @User, I have been taking a look to your design and running the simulation. We are designing a DCDC, and we are now focusing on the power stage. I noticed that you use the 5.0V/10.5V FETs, and that the current driving capability seems to be the best (checking the IDSNS50H) compared to other power devices in the technology (e.g. 20V). Was this the motivation of your choice? Also, how did you do the sizing of the power NMOS and PMOS? Considering you used 300mA output, the sizes seem to be much higher that what is needed for this current (at least from my quick calculation), is this just overdesign to make sure you are far from the maximum current density, or there are other considerations?

Not very precise, but I targeted the size of the FETs based on the efficiency I wanted.

hello Weston, thanks for replying what I called current capability is actually the spice model parameter for the current given in the PDK doc (e.g.the IDSNS50H parameter for the 5.0V/10.5V NMOS FET, when W/L = 7/0.50) how did you relate efficiency with the sizing? sorry if the question is too basic. Did you calculate this, or it comes from the RDS_ON drop in simulation for example?

Huh, not sure what that current is. Is it some saturation current or something?

hello @Weston Braun, why did you characterize a single finger here? did you extract the parasitics of that finger to account for their effect in Rds_on?

I believe the models take into account the resistance of the diffusion from the channel to the contacts. I did not extract resistance parasitic beyond what was captured in the base model. Magic was not that good at resistance extraction at the time, I dont know what the current status is.