open-source-silicon.dev

eff1.png

Just did the first full efficiency sweep for Open PMIC! Peak efficiency is ~91%, which is a bit worst than the simulated value of ~93.5%. This discrepancy is most likely because I was not able to do a full resistance extraction of the power FETs.

Looks not bad to me. In the lower part pulse skipping could have improved the efficiency. 

Which inductor did you use? What was its parasitic capacitance? I had some issues with that before.

For understanding the losses i usually recommend to do a loss over output current plot. Then the individual loss sources can be separated.

I measured the NMOS/PMOS resistance today. My simulated values were:
```NMOS: 306 um x 306 um, 36 x 36 grid, ~175 mΩ
PMOS: 372 um x 372 um, 48 x 48 grid, ~325 mΩ```

And I measured 0.6 for NMOS and 0.642 for pmos. Which is quite a difference. I never modeled metal interconnect or bond wire resistance though.

I have kinda been working on the IC bringup non-stop for the last week and have other work I need to get to. I am going to resume some testing next week

<@U017UPJEGKZ> considering both have practically the same value, i'd guess also parasitic ohmic non mosfet specific losses. Could it be the bond wires, from infineon i know they place multiple bond wires for power ics? An estimation of the metal interconnected could also help to understand the losses... What where your results? I'd love to learn from your research!

This would be very interesting to probe the bare die for resistance and see how much the bond wires contribute (my first guess is "a lot")

I talked to Tim and he pointed out that the resistance from the user project area to the bond wire pad is relatively large, even though I tried to beef it up as much as I could

I have multiple I/O pins and power connections, so I should be able to isolate one pair and use it as a kelvin sense connection

I have been busy with other stuff so no new testing results :disappointed:

I am hoping to publish a paper on it or something though. The design is not particularly novel or anything but I should be able to find something to talk about.

hello <@U017UPJEGKZ>, nice work, thanks a lot for sharing your results!
we are starting to design a circuit related to power management, and therefore your work is quite an inspiration. I was wondering if you could share details about the testing setup that you are using to characterize your chip, how do you emulate input power injection and the load experimentally? sorry if the question is too basic...

Power injection? Do you just mean the power supply? I have not done much with power supply ripple rejection yet.

I am just using a DC load and a bench power supply (with kelvin connections for more accuracy)

HMC8042 power supply and ITECH IT8511B-PLUS DC load.

test PCB is here: <https://github.com/westonb/open-pmic-pcb>

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hello Weston, amazing, thanks a lot for sharing this material
and yes, indeed, I meant power supply