I used a python script to generate a huge TCL file and then fed it into magic to generate the structure. The python script is a bit of a mess but you should be able to modify the grid size, pmos/nmos, and grid spacing (not tested this one)

alternatively I would check if the two switches I already made fit your requirements. They are already production tested (not too sure about the long term current limit due to electromigration though)

@Alfonso Cortés check this out

hello @Weston Braun, we are simulating your devices, and for the full waffle with no parasitic extraction we get R_ON roughly 0.15Ohm and 0.25Ohm for NMOS and PMOS, respectively; does this match your simulation? we want to be sure we are doing it right This gives a higher efficiency that what you targeted (I thin I read you simulated 93.5% somewhere?), the dissipated power is more than 5 times smaller... is the rest of the power lost in parasitics in the switches, metallization and bonding wire? did you calculate this beforehand or just designed for the best and then measured?

How are you calculating efficiency? This was my simulated efficiency, which includes all control power and inductor loss.

0.3W into 1.8V is ~.17A. 93% efficient is 21mW of loss. I^2R loss is ~7mW. Based on my notes I have ~8mW of bias power when idle. ~0.8mW of loss due to capacitance charging / discharging, and 4mW of loss due to the esr of the modeled inductor

I also modeled ~10m of bondwire resistance, 10m of capacitor ESR, and my current sense circuitry actually consumes a current equal to ~2% of the inductor current (~6mW)

So lots of losses beyond just the switches

to be honest I never spent that much time optimizing efficiency