For this initial test I laid out the unit cell by hand, manually created some variants for the edge cases, and then tiled them with a script. I have been busy with some other stuff this week so its been less of a priority, but I am going to refactor all of it and split the unit cell into individual layers for only one side. That way my script should be able to generate all the edge cases.

Automating the layout of the unit cell itself should be possible, but I don't want to delve that much into parsing the design rules and creating a script based on that. Would take more time than its worth right now

Has anyone asked about getting some of the higher-voltage stuff that skywater can do on their proprietary process ported to the open PDK? I'd like to be able to build a 80V tolerant gate driver and associated regulators to power an SoC for a motor driver

more specifically, I want to start with replacing the TI gate drive chip on https://github.com/madcowswe/ODriveHardware and then integrate a RiscV or Microwatt core to replace the STM32

@User can you do a video on youtube about your pmic project? I love seeing your great achievements.

Thanks for the encouragement! I definitely have plans to document the project, as well tips and tricks for the sky130 PDK in general. Right now tape-out is the highest priority, I can think about other things after the 14th 😅

@User i am curious what happened to your stepdown/pmic project.

I taped out. Just waiting for the IC. I gotta update the repo information 😅

I am going to design the PCB I need to test the IC in the next few weeks. If bringup works I guess I’ll write a paper on it

@User has left the channel

@User has left the channel

@User has left the channel

I am working on the bring-up of my sky130 buck converter now so I will be posting some more stuff soon. I just resolved some I/O issues and got the power stage running under external control. Rise time may be more than my 300Mhz scope can measure.

Just did the first full efficiency sweep for Open PMIC! Peak efficiency is ~91%, which is a bit worst than the simulated value of ~93.5%. This discrepancy is most likely because I was not able to do a full resistance extraction of the power FETs.

Hello @User, I have been taking a look to your design and running the simulation. We are designing a DCDC, and we are now focusing on the power stage. I noticed that you use the 5.0V/10.5V FETs, and that the current driving capability seems to be the best (checking the IDSNS50H) compared to other power devices in the technology (e.g. 20V). Was this the motivation of your choice? Also, how did you do the sizing of the power NMOS and PMOS? Considering you used 300mA output, the sizes seem to be much higher that what is needed for this current (at least from my quick calculation), is this just overdesign to make sure you are far from the maximum current density, or there are other considerations?

Waffle fet laid out in magic vs waffle fet in silicon!

2 buck and 3 boost DCDCs submitted to the SSCS-22 contest 😮!

Hello! did anyone here do self-heating analysis for power circuits in SKY130? if not, does anyone know where to start from? I couldn't find much refrerences...

I had to throw together a presentation on the initial test results for OpenPMIC https://docs.google.com/presentation/d/1PC-O1CdMnBhfDeytuiA5FrbG7Jn2NufCA-8EJRJ2sE0/edit?usp=sharing

the current sense circuitry, power stage, and error amplifier are decently characterized by now.

Hello @Weston Braun, Regarding your openPMIC project, we saw that you use 5 analog pads for the vssa2 reference (and 3 analog pads for SW_NODE and VDD_PWR). The pads are 25um width and the max current density for metal 5 is 2.3mA/um (from here: https://docs.google.com/spreadsheets/d/1oL6ldkQdLu-4FEQE0lX6BcgbqzYfNnd1XA8vERe0vpE/edit#gid=1059412464), which gives a bit less that the 300mA that you use in your design. Is this the calculation you did? If so, what I don't completely understand yet is the fact that the pads appear as metal 4 in the caravan file, which would lower the electromigration current density limit. Any comments on this?

This week I am working on characterizing the reverse conduction behavior of the PMOS and NMOS power switch, both to characterize the beta of the parasitic BJT and the reverse recovery charge of the switches, as neither of these are captured by the PDK models

The NMOS is in a grounded deep n-well, so the parasitic NPN collector and base are shorted. But the PMOS still has a parasitic PNP. Initial measurements seem very low. Not sure how easy it would be to check about latchup...

Hello @Weston Braun, I hope you are doing fine. From @Tim Edwards' comment in the chipathon channel, the analog supply and ground pins would be able to stand 300mA current. I was wondering: why did you choose to use analog pins for this in you openPMIC project, "wasting" several analog pins in parallel? Mostly, I'm wondering why do you use 5 pins for the ground terminal. Since we will take part in the chipathon, we will probably be unabke to count with this number of pins, but we still want to achieve 300mA, so we are looking for alternatives. We would appreciate any info you can provide!

Hello @Weston Braun, We are using the nmos_waffle from open_pmic. You isolated it, right? In the layout of the power_stage, did you connect the 2nd guard ring of the nmos to GND? Shouldn't it be connected to Drain or Vdd?

Hello @Weston Braun. You laid out very wide metal tracks on your DC-DC converter, right? Did you encounter any kind of post-tapeout DRC errors because of maximum width rules? I have to lay out ground planes for my RF submissions and they should be as wide as possible to reduce parasitic inductance.

Hello @Weston Braun, did you observe high switching current peaks in your simulations and/or measurements through your input source in your openPMIC design? what were your design considerations in this case? We get spikes up to ~1A with 2ns width between one of the state changes, but we are not sure if its a simulation artifact due to the fact that we use huge transistors without modeling the waffle parasitics (we are using your switches) or if they will atually be an issue in our design. If the second is the case, we would like to know how to take design actions, any advice?

Hello @Weston Braun, im currently working on a testing pcb taking your work as inspiration, i was wondering what are this two components for? and also what value has the ferrite bead.

I'm proud to share with you our first paper from the microelectronics group at Advanced Center for Electrical and Electronic Engineering / Universidad Tecnica Federico Santa Maria in Valparaiso, Chile, in collaboration with Joel Gak's group at Universidad Católica del Uruguay and Alejandro Oliva's group at Universidad Nacional del Sur. It focuses on the implementation and simulation of a 3-level flying capacitor DCDC converter for space applications designed using opensource tools and the Skywater 130nm opensource PDK. You can find our paper in the following link: https://ieeexplore.ieee.org/abstract/document/10087013

Hi, Could you guys please help me by suggesting some good books for power optimization?