open-source-silicon.dev

Hi all, could there be a case where Netgen shows a device mismatch despite all the pin names and fanouts seemingly being a perfect match?

<@U016V7HC58D> Can you post the netgen output?

asic_top.lvs.out

<@U016V7HC58D> So it looks like your creating a whole new chip (not something that goes on the google/efabless/skywater shuttle). Is that correct?
As <@U016EM8L91B> mentioned, the VSUBS disconnected layout port on asic_core is probably one problem.
It looks like your 2 port sram verilog is missing `clk1` and `csb1` inputs. These should probably be tied to ground if your not using the second port.
The `vssd/vssio/vccd/vddio_hvc_pad` cells have unmatched ports `DRN_HCV` and `SRC_BDY_HVC`.

I'd suggest trying to get a clean LVS result for `asic_core` first. (You can use the same netlists, just change the top cells.)

<@U017X0NM2E7> thanks for taking a look!
&gt; So it looks like your creating a whole new chip (not something that goes on the google/efabless/skywater shuttle). Is that correct?
this is correct!

those are good points! `asic_core` is LVS clean actually, but the point about the SRAM will be helpful for the design itself

also, interestingly, asic_core itself passes LVS, the top-level with  asic_core abstracted with a LEF passes LVS, but without  asic_core abstracted the whole thing does not pass

unfortunately not able to share at the moment. However, I was able to fix the problem! The issue seems to be related to the structure of the Verilog netlist. The original netlist came directly from Yosys synthesis, but if I take that Verilog file, read it in OpenROAD, and directly write it back out, the OpenROAD output passes LVS!